protected override void DoCommandAction()
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
Tile anchor = FPGA.FPGA.Instance.GetTile(AnchorLocation);
if (libElement.ResourceShape.Anchor.AnchorSliceNumber >= anchor.Slices.Count)
{
throw new ArgumentException("Too few slices on tile " + anchor.Location + ". Expecting " + libElement.ResourceShape.Anchor.AnchorSliceNumber + " but found " + anchor.Slices.Count + " slice.");
}
if (IdentifierManager.Instance.IsMatch(anchor.Location, IdentifierManager.RegexTypes.Interconnect))
{
anchor = FPGATypes.GetCLTile(anchor).FirstOrDefault();
}
if (AutoClearModuleSlot)
{
//this.FastAutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1));
AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1));
}
LibElemInst instantiation = new LibElemInst();
instantiation.AnchorLocation = AnchorLocation;
instantiation.InstanceName = Hierarchy + InstanceName;
instantiation.LibraryElementName = LibraryElementName;
instantiation.SliceNumber = libElement.ResourceShape.Anchor.AnchorSliceNumber;
instantiation.SliceName = anchor.Slices[(int)libElement.ResourceShape.Anchor.AnchorSliceNumber].SliceName;
LibraryElementInstanceManager.Instance.Add(instantiation);
// mark source as blocked
ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking();
markSrc.AnchorLocation = AnchorLocation;
markSrc.LibraryElementName = LibraryElementName;
CommandExecuter.Instance.Execute(markSrc);
SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation();
saveCmd.AddDesignConfig = false;
saveCmd.InsertPrefix = true;
saveCmd.InstanceName = InstanceName;
saveCmd.NetlistContainerName = NetlistContainerName;
CommandExecuter.Instance.Execute(saveCmd);
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
private Tile GetCorner(string identifier, FPGATypes.Direction dir)
{
Tile tile = null;
if (FPGA.FPGA.Instance.Contains(identifier))
{
tile = FPGA.FPGA.Instance.GetTile(identifier);
}
else if (identifier.Contains("_"))
{
int split = identifier.IndexOf('_');
string prefix = identifier.Substring(0, split + 1);
string suffix = identifier.Substring(split, identifier.Length - split);
tile = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => t.Location.StartsWith(prefix) && t.Location.EndsWith(suffix));
// if we can not resolve the identifer, triggger error handling in Do
if (tile == null)
{
return(null);
}
}
else
{
return(null);
}
List <Tile> otherTiles = new List <Tile>();
otherTiles.Add(tile);
// there might be more left interconnects
if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))
{
otherTiles.Add(FPGATypes.GetInterconnectTile(tile));
}
else if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
foreach (Tile o in FPGATypes.GetCLTile(tile))
{
otherTiles.Add(o);
}
}
if (dir == FPGATypes.Direction.West)
{
int min = otherTiles.Min(t => t.TileKey.X);
return(otherTiles.FirstOrDefault(t => t.TileKey.X == min));
}
else if (dir == FPGATypes.Direction.East)
{
int max = otherTiles.Max(t => t.TileKey.X);
return(otherTiles.FirstOrDefault(t => t.TileKey.X == max));
}
else
{
throw new ArgumentException(GetType().Name + ".GetCorner only supports East and West");
}
}
public TileViewForm(Tile tile)
{
InitializeComponent();
m_tile = tile;
Settings.StoredPreferences.Instance.GUISettings.Open(this);
List <Tile> tiles = new List <Tile>();
tiles.Add(m_tile);
if (IdentifierManager.Instance.IsMatch(m_tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
tiles.AddRange(FPGATypes.GetCLTile(m_tile));
}
if (IdentifierManager.Instance.IsMatch(m_tile.Location, IdentifierManager.RegexTypes.CLB))
{
Tile interconnect = FPGATypes.GetInterconnectTile(m_tile);
tiles.Add(interconnect);
foreach (Tile clb in FPGATypes.GetCLTile(interconnect))
{
if (!tiles.Contains(clb))
{
tiles.Add(clb);
}
}
}
foreach (Tile t in tiles)
{
TabPage page = new TabPage();
page.Text = t.Location;
TileViewCtrl viewCtrl = new TileViewCtrl(t);
viewCtrl.Dock = DockStyle.Fill;
page.Controls.Add(viewCtrl);
m_tabTop.TabPages.Add(page);
}
}
protected override void DoCommandAction()
{
if (!RAMSelectionManager.Instance.HasMappings)
{
RAMSelectionManager.Instance.UpdateMapping();
}
List <Tile> expansion = new List <Tile>();
// get tiles to add
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles())
{
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(t);
if (intTile.LocationX == t.LocationX && intTile.LocationY == t.LocationY && IdentifierManager.Instance.IsMatch(intTile.Location, IdentifierManager.RegexTypes.Interconnect))
{
if (AddToSelection(intTile))
{
expansion.Add(intTile);
}
foreach (Tile clbTile in FPGATypes.GetCLTile(intTile))
{
if (AddToSelection(clbTile))
{
expansion.Add(clbTile);
}
}
}
}
if (IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect))
{
foreach (Tile clbTile in FPGATypes.GetCLTile(t))
{
if (clbTile.LocationX == t.LocationX && clbTile.LocationY == t.LocationY && IdentifierManager.Instance.IsMatch(clbTile.Location, IdentifierManager.RegexTypes.CLB))
{
if (AddToSelection(clbTile))
{
expansion.Add(clbTile);
}
}
}
}
if (RAMSelectionManager.Instance.HasMapping(t))
{
foreach (Tile ramBlockMember in RAMSelectionManager.Instance.GetRamBlockMembers(t))
{
if (AddToSelection(ramBlockMember))
{
expansion.Add(ramBlockMember);
}
}
}
}
// expand selection
foreach (Tile t in expansion)
{
TileSelectionManager.Instance.AddToSelection(t.TileKey, false);
}
TileSelectionManager.Instance.SelectionChanged();
}
private void DrawNonRAMTile(Tile tile, Graphics graphicsObj, bool addIncrementForSelectedTiles, bool addIncrementForUserSelectedTiles)
{
int upperLeftX = 0;
int upperLeftY = 0;
int widthScale = 1;
int heightScale = 1;
if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))
{
Tile intTile = FPGATypes.GetInterconnectTile(tile);
switch (FPGA.FPGA.Instance.Family)
{
case FPGATypes.FPGAFamily.Artix7:
case FPGATypes.FPGAFamily.Kintex7:
case FPGATypes.FPGAFamily.Virtex7:
case FPGATypes.FPGAFamily.Zynq:
{
if (FPGATypes.IsOrientedMatch(tile.Location, IdentifierManager.RegexTypes.CLB_left))
{
// CLBLL_L_X INT_L_X
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
widthScale = 2;
}
else
{
upperLeftX = intTile.TileKey.X * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
widthScale = 2;
}
break;
}
case FPGATypes.FPGAFamily.UltraScale:
{
widthScale = FPGATypes.GetCLTile(intTile).Count() + 1;
if (FPGATypes.IsOrientedMatch(tile.Location, IdentifierManager.RegexTypes.CLB_left))
{
// CLBLL_L_X INT_L_X
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
}
else
{
upperLeftX = (intTile.TileKey.X - (widthScale == 2 ? 0 : 1)) * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
}
break;
}
default:
{
upperLeftX = intTile.TileKey.X * m_view.TileSize;
upperLeftY = intTile.TileKey.Y * m_view.TileSize;
// double size of the rectangle
widthScale = 2;
break;
}
}
}
else if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.Interconnect))
{
// interconnect tiles for CLB have no tiles
return;
}
else
{
upperLeftX = tile.TileKey.X * m_view.TileSize;
upperLeftY = tile.TileKey.Y * m_view.TileSize;
}
m_rect.X = upperLeftX - 1;
m_rect.Y = upperLeftY - 1;
m_rect.Width = (widthScale * (m_view.TileSize - 1) + widthScale) - 2;
m_rect.Height = (heightScale * (m_view.TileSize - 1) + heightScale) - 2;
// default color maybde overwritten
m_sb.Color = m_view.GetColor(tile, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles);
graphicsObj.FillRectangle(m_sb, m_rect);
}