public CortexA7(Machine machine, GIC gic, ulong genericTimerCompareValue, Endianess endianness = Endianess.LittleEndian) : base("cortex-a15", machine, endianness)
{
genericTimer = new CortexAGenericTimer(machine, gic, genericTimerCompareValue);
}
protected BaseRiscV(IRiscVTimeProvider timeProvider, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness) : base(hartId, cpuType, machine, endianness, bitness)
{
HartId = hartId;
this.timeProvider = timeProvider;
this.privilegeArchitecture = privilegeArchitecture;
ShouldEnterDebugMode = true;
nonstandardCSR = new Dictionary <ulong, Tuple <Func <ulong>, Action <ulong> > >();
customInstructionsMapping = new Dictionary <ulong, Action <UInt64> >();
architectureSets = DecodeArchitecture(cpuType);
EnableArchitectureVariants();
}
public IbexRiscV32(Machine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_11, Endianess endianness = Endianess.LittleEndian, string cpuType = "rv32imcu", bool allowUnalignedAccesses = true) : base(timeProvider, cpuType, machine, hartId, privilegeArchitecture, endianness, allowUnalignedAccesses: allowUnalignedAccesses, interruptMode: InterruptMode.Vectored)
{
}
public RiscV32(IRiscVTimeProvider timeProvider, string cpuType, Machine machine, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_11, Endianess endianness = Endianess.LittleEndian, ulong?nmiVectorAddress = null, uint?nmiVectorLength = null)
: base(timeProvider, hartId, cpuType, machine, privilegeArchitecture, endianness, CpuBitness.Bits32, nmiVectorAddress, nmiVectorLength)
{
}
public RiscV32(IRiscVTimeProvider timeProvider, string cpuType, Machine machine, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_11, Endianess endianness = Endianess.LittleEndian, ulong?nmiVectorAddress = null, uint?nmiVectorLength = null, bool allowUnalignedAccesses = false, InterruptMode interruptMode = InterruptMode.Auto)
: base(timeProvider, hartId, cpuType, machine, privilegeArchitecture, endianness, CpuBitness.Bits32, nmiVectorAddress, nmiVectorLength, allowUnalignedAccesses, interruptMode)
{
}
public CortexA7(Machine machine, GIC gic, long genericTimerCompareValue, Endianess endianness = Endianess.LittleEndian) : base("cortex-a15", machine, endianness)
{
genericTimer = new CortexAGenericTimer(machine, gic, genericTimerCompareValue);
}
public RiscV64(IRiscVTimeProvider timeProvider, string cpuType, Machine machine, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_10, Endianess endianness = Endianess.LittleEndian) : base(timeProvider, hartId, cpuType, machine, privilegeArchitecture, endianness, CpuBitness.Bits64)
{
}
protected BaseRiscV(IRiscVTimeProvider timeProvider, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness, ulong?nmiVectorAddress = null, uint?nmiVectorLength = null, bool allowUnalignedAccesses = false, InterruptMode interruptMode = InterruptMode.Auto)
: base(hartId, cpuType, machine, endianness, bitness)
{
HartId = hartId;
this.timeProvider = timeProvider;
this.privilegeArchitecture = privilegeArchitecture;
shouldEnterDebugMode = true;
nonstandardCSR = new Dictionary <ulong, NonstandardCSR>();
customInstructionsMapping = new Dictionary <ulong, Action <UInt64> >();
this.NMIVectorLength = nmiVectorLength;
this.NMIVectorAddress = nmiVectorAddress;
architectureSets = DecodeArchitecture(cpuType);
EnableArchitectureVariants();
if (this.NMIVectorAddress.HasValue && this.NMIVectorLength.HasValue && this.NMIVectorLength > 0)
{
this.Log(LogLevel.Noisy, "Non maskable interrupts enabled with paramters: {0} = {1}, {2} = {3}",
nameof(this.NMIVectorAddress), this.NMIVectorAddress, nameof(this.NMIVectorLength), this.NMIVectorLength);
TlibSetNmiVector(this.NMIVectorAddress.Value, this.NMIVectorLength.Value);
}
else
{
this.Log(LogLevel.Noisy, "Non maskable interrupts disabled");
TlibSetNmiVector(0, 0);
}
TlibAllowUnalignedAccesses(allowUnalignedAccesses ? 1 : 0);
try
{
this.interruptMode = interruptMode;
TlibSetInterruptMode((int)interruptMode);
}
catch (CpuAbortException)
{
throw new ConstructionException(string.Format("Unsupported interrupt mode: 0x{0:X}", interruptMode));
}
UserState = new Dictionary <string, object>();
}
public Ri5cy(Machine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_10, Endianess endianness = Endianess.LittleEndian) : base(timeProvider, "rv32imc", machine, hartId, privilegeArchitecture, endianness)
{
// enable all interrupt sources
MIE = 0xffffffff;
TlibSetCsrValidation(0);
// register custom CSRs
// TODO: add support for HW loops
RegisterCSR((ulong)0x7b0, () => 0u, _ => {}); //lpstart0
RegisterCSR((ulong)0x7b1, () => 0u, _ => {}); //lpend1
RegisterCSR((ulong)0x7b2, () => 0u, _ => {}); //lpcount0
RegisterCSR((ulong)0x7b4, () => 0u, _ => {}); //lpstart1
RegisterCSR((ulong)0x7b5, () => 0u, _ => {}); //lpend1
RegisterCSR((ulong)0x7b6, () => 0u, _ => {}); //lpcount1
}
public Arm(string cpuType, Machine machine, Endianess endianness = Endianess.LittleEndian) : base(cpuType, machine, endianness)
{
}
private void HandleConfigurationChange(int width, int height, Backends.Display.PixelFormat format, ELFSharp.ELF.Endianess endianess)
{
converter = PixelManipulationTools.GetConverter(format, endianess, Backends.Display.PixelFormat.ARGB8888, ELFSharp.ELF.Endianess.LittleEndian);
frameSize = width * height * 4;
}
public Sparc(string cpuType, Machine machine, Endianess endianness = Endianess.BigEndian): base(cpuType, machine, endianness)
{
Init();
}
protected BaseRiscV(IRiscVTimeProvider timeProvider, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness, ulong?nmiVectorAddress = null, uint?nmiVectorLength = null, bool allowUnalignedAccesses = false)
: base(hartId, cpuType, machine, endianness, bitness)
{
HartId = hartId;
this.timeProvider = timeProvider;
this.privilegeArchitecture = privilegeArchitecture;
ShouldEnterDebugMode = true;
nonstandardCSR = new Dictionary <ulong, Tuple <Func <ulong>, Action <ulong> > >();
customInstructionsMapping = new Dictionary <ulong, Action <UInt64> >();
this.NMIVectorLength = nmiVectorLength;
this.NMIVectorAddress = nmiVectorAddress;
architectureSets = DecodeArchitecture(cpuType);
EnableArchitectureVariants();
if (this.NMIVectorAddress.HasValue && this.NMIVectorLength.HasValue && this.NMIVectorLength > 0)
{
this.Log(LogLevel.Noisy, "Non maskable interrupts enabled with paramters: {0} = {1}, {2} = {3}",
nameof(this.NMIVectorAddress), this.NMIVectorAddress, nameof(this.NMIVectorLength), this.NMIVectorLength);
TlibSetNmiVector(this.NMIVectorAddress.Value, this.NMIVectorLength.Value);
}
else
{
this.Log(LogLevel.Noisy, "Non maskable interrupts disabled");
TlibSetNmiVector(0, 0);
}
TlibAllowUnalignedAccesses(allowUnalignedAccesses ? 1 : 0);
UserState = new Dictionary <string, object>();
}
public RiscV64(CoreLevelInterruptor clint, string cpuType, Machine machine, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_10, Endianess endianness = Endianess.LittleEndian) : base(clint, hartId, cpuType, machine, privilegeArchitecture, endianness, CpuBitness.Bits64)
{
}
public CV32E40P(Machine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_11, Endianess endianness = Endianess.LittleEndian, string cpuType = "rv32imfc")
: base(null, cpuType, machine, hartId, privilegeArchitecture, endianness)
{
RegisterCSR((ulong)CustomCSR.PerformanceCounterMode, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.StackCheckEnable, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.StackBase, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.StackEnd, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.HardwareLoop0Start, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.HardwareLoop0End, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.HardwareLoop0Counter, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.HardwareLoop1Start, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.HardwareLoop1End, () => 0u, _ => { });
RegisterCSR((ulong)CustomCSR.HardwareLoop1Counter, () => 0u, _ => { });
InstallCustomInstruction(pattern: "FFFFFFFFFFFFBBBBB000DDDDD0001011", handler: opcode => LoadRegisterImmediate(opcode, Width.Byte, BitExtension.Sign, "p.lb rD, Imm(rs1!)"));
InstallCustomInstruction(pattern: "FFFFFFFFFFFFBBBBB100DDDDD0001011", handler: opcode => LoadRegisterImmediate(opcode, Width.Byte, BitExtension.Zero, "p.lbu rD, Imm(rs1!)"));
InstallCustomInstruction(pattern: "FFFFFFFFFFFFBBBBB001DDDDD0001011", handler: opcode => LoadRegisterImmediate(opcode, Width.HalfWord, BitExtension.Sign, "p.lh rD, Imm(rs1!)"));
InstallCustomInstruction(pattern: "FFFFFFFFFFFFBBBBB101DDDDD0001011", handler: opcode => LoadRegisterImmediate(opcode, Width.HalfWord, BitExtension.Zero, "p.lhu rD, Imm(rs1!)"));
InstallCustomInstruction(pattern: "FFFFFFFFFFFFBBBBB010DDDDD0001011", handler: opcode => LoadRegisterImmediate(opcode, Width.Word, BitExtension.Zero, "p.lw rD, Imm(rs1!)"));
InstallCustomInstruction(pattern: "0000000FFFFFBBBBB111DDDDD0001011", handler: opcode => LoadRegisterRegister(opcode, Width.Byte, BitExtension.Sign, postIncrement: true, log: "p.lb rD, rs2(rs1!)"));
InstallCustomInstruction(pattern: "0100000FFFFFBBBBB111DDDDD0001011", handler: opcode => LoadRegisterRegister(opcode, Width.Byte, BitExtension.Zero, postIncrement: true, log: "p.lbu rD, rs2(rs1!)"));
InstallCustomInstruction(pattern: "0001000FFFFFBBBBB111DDDDD0001011", handler: opcode => LoadRegisterRegister(opcode, Width.HalfWord, BitExtension.Sign, postIncrement: true, log: "p.lh rD, rs2(rs1!)"));
InstallCustomInstruction(pattern: "0101000FFFFFBBBBB111DDDDD0001011", handler: opcode => LoadRegisterRegister(opcode, Width.HalfWord, BitExtension.Zero, postIncrement: true, log: "p.lhu rD, rs2(rs1!)"));
InstallCustomInstruction(pattern: "0010000FFFFFBBBBB111DDDDD0001011", handler: opcode => LoadRegisterRegister(opcode, Width.Word, BitExtension.Zero, postIncrement: true, log: "p.lw rD, rs2(rs1!)"));
InstallCustomInstruction(pattern: "0000000FFFFFBBBBB111DDDDD0000011", handler: opcode => LoadRegisterRegister(opcode, Width.Byte, BitExtension.Sign, "p.lb rD, rs2(rs1)"));
InstallCustomInstruction(pattern: "0100000FFFFFBBBBB111DDDDD0000011", handler: opcode => LoadRegisterRegister(opcode, Width.Byte, BitExtension.Zero, "p.lbu rD, rs2(rs1)"));
InstallCustomInstruction(pattern: "0001000FFFFFBBBBB111DDDDD0000011", handler: opcode => LoadRegisterRegister(opcode, Width.HalfWord, BitExtension.Sign, "p.lh rD, rs2(rs1)"));
InstallCustomInstruction(pattern: "0101000FFFFFBBBBB111DDDDD0000011", handler: opcode => LoadRegisterRegister(opcode, Width.HalfWord, BitExtension.Zero, "p.lhu rD, rs2(rs1)"));
InstallCustomInstruction(pattern: "0010000FFFFFBBBBB111DDDDD0000011", handler: opcode => LoadRegisterRegister(opcode, Width.Word, BitExtension.Zero, "p.lw rD, rs2(rs1)"));
InstallCustomInstruction(pattern: "FFFFFFFSSSSSBBBBB000FFFFF0101011", handler: opcode => StoreRegisterImmediate(opcode, Width.Byte, "p.sb rs2, Imm(rs1!)"));
InstallCustomInstruction(pattern: "FFFFFFFSSSSSBBBBB001FFFFF0101011", handler: opcode => StoreRegisterImmediate(opcode, Width.HalfWord, "p.sh rs2, Imm(rs1!)"));
InstallCustomInstruction(pattern: "FFFFFFFSSSSSBBBBB010FFFFF0101011", handler: opcode => StoreRegisterImmediate(opcode, Width.Word, "p.sw rs2, Imm(rs1!)"));
InstallCustomInstruction(pattern: "0000000SSSSSBBBBB100FFFFF0101011", handler: opcode => StoreRegisterRegister(opcode, Width.Byte, postIncrement: true, log: "p.sb rs2, rs3(rs1!)"));
InstallCustomInstruction(pattern: "0000000SSSSSBBBBB101FFFFF0101011", handler: opcode => StoreRegisterRegister(opcode, Width.HalfWord, postIncrement: true, log: "p.sh rs2, rs3(rs1!)"));
InstallCustomInstruction(pattern: "0000000SSSSSBBBBB110FFFFF0101011", handler: opcode => StoreRegisterRegister(opcode, Width.Word, postIncrement: true, log: "p.sw rs2, rs3(rs1!)"));
InstallCustomInstruction(pattern: "0000000SSSSSBBBBB100FFFFF0100011", handler: opcode => StoreRegisterRegister(opcode, Width.Byte, "p.sb rs2, rs3(rs1)"));
InstallCustomInstruction(pattern: "0000000SSSSSBBBBB101FFFFF0100011", handler: opcode => StoreRegisterRegister(opcode, Width.HalfWord, "p.sh rs2, rs3(rs1)"));
InstallCustomInstruction(pattern: "0000000SSSSSBBBBB110FFFFF0100011", handler: opcode => StoreRegisterRegister(opcode, Width.Word, "p.sw rs2, rs3(rs1)"));
InstallCustomInstruction(pattern: "0000010RRRRRSSSSS100DDDDD0110011", handler: opcode => CompareRegisters(opcode, ComparisonType.Min, Sign.Signed, "p.min rD, rs1, rs2"));
InstallCustomInstruction(pattern: "0000010RRRRRSSSSS101DDDDD0110011", handler: opcode => CompareRegisters(opcode, ComparisonType.Min, Sign.Unsigned, "p.minu rD, rs1, rs2"));
InstallCustomInstruction(pattern: "0000010RRRRRSSSSS110DDDDD0110011", handler: opcode => CompareRegisters(opcode, ComparisonType.Max, Sign.Signed, "p.max rD, rs1, rs2"));
InstallCustomInstruction(pattern: "0000010RRRRRSSSSS111DDDDD0110011", handler: opcode => CompareRegisters(opcode, ComparisonType.Max, Sign.Unsigned, "p.maxu rD, rs1, rs2"));
InstallCustomInstruction(pattern: "11LLLLLLLLLLSSSSS000DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Extract, Width.Word, Sign.Signed, "p.extract rD, rs1, Is3, Is2"));
InstallCustomInstruction(pattern: "11LLLLLLLLLLSSSSS001DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Extract, Width.Word, Sign.Unsigned, "p.extractu rD, rs1, Is3, Is2"));
InstallCustomInstruction(pattern: "000100000000SSSSS100DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Extract, Width.HalfWord, Sign.Signed, "p.exths rD, rs1"));
InstallCustomInstruction(pattern: "000100000000SSSSS101DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Extract, Width.HalfWord, Sign.Unsigned, "p.exthz rD, rs1"));
InstallCustomInstruction(pattern: "000100000000SSSSS110DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Extract, Width.Byte, Sign.Signed, "p.extbs rD, rs1"));
InstallCustomInstruction(pattern: "000100000000SSSSS111DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Extract, Width.Byte, Sign.Unsigned, "p.extbz rD, rs1"));
InstallCustomInstruction(pattern: "11LLLLLLLLLLSSSSS010DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Insert, Width.Word, Sign.Unsigned, "p.insert rD, rs1, Is3, Is2"));
InstallCustomInstruction(pattern: "11LLLLLLLLLLSSSSS011DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Clear, Width.Word, Sign.Unsigned, "p.bclr rD, rs1, Is3, Is2"));
InstallCustomInstruction(pattern: "11LLLLLLLLLLSSSSS100DDDDD0110011", handler: opcode => ManipulateBitsInRegister(opcode, Operation.Set, Width.Word, Sign.Unsigned, "p.bset rD, rs1, Is3, Is2"));
InstallCustomInstruction(pattern: "JJJJJJJIIIIISSSSS010JJJJJ1100011", handler: opcode => BranchIf(opcode, Equality.Equal, "p.beqimm rs1, Imm5, Imm12"));
InstallCustomInstruction(pattern: "JJJJJJJIIIIISSSSS011JJJJJ1100011", handler: opcode => BranchIf(opcode, Equality.NotEqual, "p.bneimm rs1, Imm5, Imm12"));
InstallCustomInstruction(pattern: "0100001----------001-----0110011", handler: _ => LogUnsupported("p.msu rD, rs1, rs2"));
InstallCustomInstruction(pattern: "0100001----------000-----0110011", handler: _ => LogUnsupported("p.mac rD, rs1, rs2"));
InstallCustomInstruction(pattern: "00---------------001-----1011011", handler: _ => LogUnsupported("p.macuN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "00---------------110-----1011011", handler: _ => LogUnsupported("p.mac.zh.zl"));
InstallCustomInstruction(pattern: "00---------------100-----1011011", handler: _ => LogUnsupported("p.mac.zl.zl"));
InstallCustomInstruction(pattern: "00---------------111-----1011011", handler: _ => LogUnsupported("p.mac.zh.zh"));
InstallCustomInstruction(pattern: "00---------------101-----1011011", handler: _ => LogUnsupported("p.mac.zl.zh"));
InstallCustomInstruction(pattern: "01---------------100-----1011011", handler: _ => LogUnsupported("p.mac.zl.sl"));
InstallCustomInstruction(pattern: "------------000000000000-1111011", handler: _ => LogUnsupported("lp.starti L, uimmL"));
InstallCustomInstruction(pattern: "------------000000010000-1111011", handler: _ => LogUnsupported("lp.endi L, uimmL"));
InstallCustomInstruction(pattern: "00---------------010-----1011011", handler: _ => LogUnsupported("p.addN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "1100000----------010-----1011011", handler: _ => LogUnsupported("p.adduNr rD, rs1, rs"));
InstallCustomInstruction(pattern: "-----------------1000000-1111011", handler: _ => LogUnsupported("lp.setup L, rs1, uimmL"));
InstallCustomInstruction(pattern: "-----------------1010000-1111011", handler: _ => LogUnsupported("lp.setupi L, uimmS, uimmL"));
InstallCustomInstruction(pattern: "000000000000-----0100000-1111011", handler: _ => LogUnsupported("lp.count L, rs1"));
InstallCustomInstruction(pattern: "00---------------011-----1011011", handler: _ => LogUnsupported("p.subN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "10---------------011-----1011011", handler: _ => LogUnsupported("p.subuN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "10---------------000-----1011011", handler: _ => LogUnsupported("p.mulsN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "01---------------000-----1011011", handler: _ => LogUnsupported("p.mulhhuN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "11---------------000-----1011011", handler: _ => LogUnsupported("p.mulhhsN rD, rs1, rs2, Is3"));
InstallCustomInstruction(pattern: "1000000----------100-----0110011", handler: _ => LogUnsupported("p.bsetr rD, rs1, rs2"));
InstallCustomInstruction(pattern: "000100000000-----001-----0110011", handler: _ => LogUnsupported("p.fl1 rD, rs1"));
InstallCustomInstruction(pattern: "-----------------110-----0000011", handler: _ => LogUnsupported("p.elw"));
}
public Sparc(string cpuType, Machine machine, Endianess endianness = Endianess.BigEndian) : base(cpuType, machine, endianness)
{
Init();
}
protected BaseRiscV(CoreLevelInterruptor clint, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness) : base(cpuType, machine, endianness, bitness)
{
HartId = hartId;
clint.RegisterCPU(this);
this.clint = clint;
this.privilegeArchitecture = privilegeArchitecture;
var architectureSets = DecodeArchitecture(cpuType);
foreach (var @set in architectureSets)
{
if (Enum.IsDefined(typeof(InstructionSet), set))
{
TlibAllowFeature((uint)set);
}
else if ((int)set == 'G' - 'A')
{
//G is a wildcard denoting multiple instruction sets
foreach (var gSet in new[] { InstructionSet.I, InstructionSet.M, InstructionSet.F, InstructionSet.D, InstructionSet.A })
{
TlibAllowFeature((uint)gSet);
}
}
else
{
this.Log(LogLevel.Warning, $"Undefined instruction set: {char.ToUpper((char)(set + 'A'))}.");
}
}
TlibSetPrivilegeArchitecture109(privilegeArchitecture == PrivilegeArchitecture.Priv1_09 ? 1 : 0u);
}
public RiscV(string cpuType, long frequency, Machine machine, PrivilegeMode privilegeMode = PrivilegeMode.Priv1_10, Endianess endianness = Endianess.LittleEndian) : base(cpuType, machine, endianness)
{
InnerTimer = new ComparingTimer(machine.ClockSource, frequency, enabled: true, eventEnabled: true);
intTypeToVal = new TwoWayDictionary <int, IrqType>();
intTypeToVal.Add(0, IrqType.MachineTimerIrq);
intTypeToVal.Add(1, IrqType.MachineExternalIrq);
intTypeToVal.Add(2, IrqType.MachineSoftwareInterrupt);
var architectureSets = DecodeArchitecture(cpuType);
foreach (var @set in architectureSets)
{
if (Enum.IsDefined(typeof(InstructionSet), set))
{
TlibAllowFeature((uint)set);
}
else if ((int)set == 'G' - 'A')
{
//G is a wildcard denoting multiple instruction sets
foreach (var gSet in new [] { InstructionSet.I, InstructionSet.M, InstructionSet.F, InstructionSet.D, InstructionSet.A })
{
TlibAllowFeature((uint)gSet);
}
}
else
{
this.Log(LogLevel.Warning, $"Undefined instruction set: {char.ToUpper((char)(set + 'A'))}.");
}
}
TlibSetPrivilegeMode109(privilegeMode == PrivilegeMode.Priv1_09 ? 1 : 0u);
}