private ProcessPool.ToolBatch CreateBatch(EFlowStep steps)
{
var bat = ProcessPool.Instance.CreateBatch();
if (steps.HasFlag(EFlowStep.XST))
{
XST.SaveToXSTScriptAndAddToBatch(Project, bat, XSTScriptPath, XSTLogPath);
}
if (steps.HasFlag(EFlowStep.NGDBuild))
{
NGDBuild.AddToBatch(Project, bat);
}
if (steps.HasFlag(EFlowStep.Map))
{
Map.AddToBatch(Project, bat);
}
if (steps.HasFlag(EFlowStep.PAR))
{
PAR.AddToBatch(Project, bat);
}
if (steps.HasFlag(EFlowStep.TRCE))
{
TRCE.AddToBatch(Project, bat);
}
return(bat);
}
/// <summary>
/// Synthesizes the design.
/// </summary>
/// <param name="destPath">target path which will contain the generated files</param>
/// <param name="designName">name of the design</param>
/// <param name="info">ISE information</param>
/// <param name="twinProject">optional twin project</param>
/// <param name="step">what stages of the overall flow to execute</param>
/// <returns>the generated ISE project</returns>
public XilinxProject Synthesize(string destPath, string designName, ISEInfo info,
IProject twinProject = null, EFlowStep step = EFlowStep.HDLGenAndIPCores)
{
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(destPath, designName)
{
TwinProject = twinProject
};
project.ISEVersion = info.VersionTag;
if (info.Path == null)
{
project.SkipIPCoreSynthesis = true;
}
else
{
project.ISEBinPath = info.Path;
}
project.PutProperty(EXilinxProjectProperties.DeviceFamily, Device.GetFamily());
project.PutProperty(EXilinxProjectProperties.Device, Device);
project.PutProperty(EXilinxProjectProperties.Package, Package);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, SpeedGrade);
project.SetVHDLProfile();
if (!step.HasFlag(EFlowStep.IPCores))
{
project.SkipIPCoreSynthesis = true;
}
project.TopLevelComponent = TopLevelComponent.Descriptor;
CreateUCF(project);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(GetComponentSet(), codeGen);
project.Save();
if (step.HasFlag(EFlowStep.XST) ||
step.HasFlag(EFlowStep.NGDBuild) ||
step.HasFlag(EFlowStep.Map) ||
step.HasFlag(EFlowStep.PAR) ||
step.HasFlag(EFlowStep.TRCE))
{
var flow = project.ConfigureFlow(TopLevelComponent);
flow.Start(step);
}
return(project);
}
private ProcessPool.ToolBatch CreateBatch(EFlowStep steps)
{
var bat = ProcessPool.Instance.CreateBatch();
if (steps.HasFlag(EFlowStep.XST))
XST.SaveToXSTScriptAndAddToBatch(Project, bat, XSTScriptPath, XSTLogPath);
if (steps.HasFlag(EFlowStep.NGDBuild))
NGDBuild.AddToBatch(Project, bat);
if (steps.HasFlag(EFlowStep.Map))
Map.AddToBatch(Project, bat);
if (steps.HasFlag(EFlowStep.PAR))
PAR.AddToBatch(Project, bat);
if (steps.HasFlag(EFlowStep.TRCE))
TRCE.AddToBatch(Project, bat);
return bat;
}
/// <summary>
/// Synthesizes the design.
/// </summary>
/// <param name="destPath">target path which will contain the generated files</param>
/// <param name="designName">name of the design</param>
/// <param name="info">ISE information</param>
/// <param name="twinProject">optional twin project</param>
/// <param name="step">what stages of the overall flow to execute</param>
/// <returns>the generated ISE project</returns>
public XilinxProject Synthesize(string destPath, string designName, ISEInfo info,
IProject twinProject = null, EFlowStep step = EFlowStep.HDLGenAndIPCores)
{
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(destPath, designName)
{
TwinProject = twinProject
};
project.ISEVersion = info.VersionTag;
if (info.Path == null)
project.SkipIPCoreSynthesis = true;
else
project.ISEBinPath = info.Path;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, Device.GetFamily());
project.PutProperty(EXilinxProjectProperties.Device, Device);
project.PutProperty(EXilinxProjectProperties.Package, Package);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, SpeedGrade);
project.SetVHDLProfile();
if (!step.HasFlag(EFlowStep.IPCores))
project.SkipIPCoreSynthesis = true;
project.TopLevelComponent = TopLevelComponent.Descriptor;
CreateUCF(project);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(GetComponentSet(), codeGen);
project.Save();
if (step.HasFlag(EFlowStep.XST) ||
step.HasFlag(EFlowStep.NGDBuild) ||
step.HasFlag(EFlowStep.Map) ||
step.HasFlag(EFlowStep.PAR) ||
step.HasFlag(EFlowStep.TRCE))
{
var flow = project.ConfigureFlow(TopLevelComponent);
flow.Start(step);
}
return project;
}
