public void DEV9irq(UInt16 cause, int cycles)
{
Log_Verb("DEV9irq " + cause.ToString("X") + ", " + spd.regIntrMask.ToString("X"));
spd.regIntStat |= cause;
if (cycles < 1)
{
DEV9Header.DEV9irq(1);
}
else
{
DEV9Header.DEV9irq(cycles);
}
}
public void SPEED_Write16(uint addr, ushort value)
{
switch (addr)
{
case SPEED_Header.SPD_R_DMA_CTRL:
Log_Verb("SPD_R_DMA_CTRL 16bit write " + value.ToString("X"));
regDMACtrl = value;
if (dmaSMAP)
{
Log_Verb("SPD_R_DMA_CTRL DMA For SMAP");
}
else
{
Log_Verb("SPD_R_DMA_CTRL DMA For ATA");
}
if ((value & SPEED_Header.SPD_DMA_FASTEST) != 0)
{
Log_Verb("SPD_R_DMA_CTRL Fastest DMA Mode");
}
else
{
Log_Verb("SPD_R_DMA_CTRL Slower DMA Mode");
}
if ((value & SPEED_Header.SPD_DMA_WIDE) != 0)
{
Log_Verb("SPD_R_DMA_CTRL Wide(32bit) DMA Mode Set");
}
else
{
Log_Verb("SPD_R_DMA_CTRL 16bit DMA Mode");
}
if ((value & SPEED_Header.SPD_DMA_PAUSE) != 0)
{
Log_Error("SPD_R_DMA_CTRL Pause DMA");
}
if ((value & 0b1111_1111_1110_0000) != 0)
{
Log_Error("SPD_R_DMA_CTRL Unkown value written" + value.ToString("X"));
}
return;
case SPEED_Header.SPD_R_INTR_MASK:
Log_Verb("SPD_R_INTR_MASK16 16bit write " + value.ToString("X") + " , checking for masked/unmasked interrupts");
if ((regIntrMask != value) && (((regIntrMask | value) & regIntStat) != 0))
{
Log_Verb("SPD_R_INTR_MASK16 firing unmasked interrupts");
DEV9Header.DEV9irq(1);
}
regIntrMask = value;
return;
case SPEED_Header.SPD_R_XFR_CTRL:
Log_Verb("SPD_R_XFR_CTRL 16bit write " + value.ToString("X"));
regXFRCtrl = value;
if (xfrWrite)
{
Log_Verb("SPD_R_XFR_CTRL Set Write");
}
else
{
Log_Verb("SPD_R_XFR_CTRL Set Read");
}
if ((value & (1 << 1)) != 0)
{
Log_Verb("SPD_R_XFR_CTRL Unkown Bit 1");
}
if ((value & (1 << 2)) != 0)
{
Log_Verb("SPD_R_XFR_CTRL Unkown Bit 2");
}
if (xfrDMAEN)
{
Log_Verb("SPD_R_XFR_CTRL For DMA Enabled");
}
else
{
Log_Verb("SPD_R_XFR_CTRL For DMA Disabled");
}
if ((value & 0b1111_1111_0111_1000) != 0)
{
Log_Error("SPD_R_XFR_CTRL Unkown value written" + value.ToString("X"));
}
break;
case SPEED_Header.SPD_R_DBUF_STAT:
Log_Verb("SPD_R_38 16bit write " + value.ToString("X"));
if ((value & SPEED_Header.SPD_DBUF_RESET_FIFO) != 0)
{
Log_Verb("SPD_R_XFR_CTRL Reset FIFO");
bytesWriteFIFO = 0;
bytesReadFIFO = 0;
xfrWrite = false; //??
ifRead = true; //??
FIFOIntr();
}
if (value != 3)
{
Log_Error("SPD_R_38 16bit write " + value.ToString("X") + " Which != 3!!!");
}
break;
case SPEED_Header.SPD_R_IF_CTRL: //ATA only?
Log_Verb("SPD_R_IF_CTRL 16bit write " + value.ToString("X"));
regIFCtrl = value;
#region regIFCtrl
if ((regIFCtrl & SPEED_Header.SPD_IF_UDMA) != 0)
{
Log_Verb("IF_CTRL UDMA Enabled");
}
else
{
Log_Verb("IF_CTRL UDMA Disabled");
}
if (ifRead)
{
Log_Verb("IF_CTRL DMA Is ATA Read");
}
else
{
Log_Verb("IF_CTRL DMA Is ATA Write");
}
if (ifDMAEN)
{
Log_Verb("IF_CTRL ATA DMA Enabled");
if (ifRead) //Semi async
{
HDDWriteFIFO(); //Yes this is not a typo
}
else
{
HDDReadFIFO();
}
FIFOIntr();
}
else
{
Log_Verb("IF_CTRL ATA DMA Disabled");
}
if ((regIFCtrl & (1 << 3)) != 0)
{
Log_Verb("IF_CTRL Unkown Bit 3 Set");
}
if ((regIFCtrl & (1 << 4)) != 0)
{
Log_Error("IF_CTRL Unkown Bit 4 Set");
}
if ((regIFCtrl & (1 << 5)) != 0)
{
Log_Error("IF_CTRL Unkown Bit 5 Set");
}
if ((regIFCtrl & SPEED_Header.SPD_IF_HDD_RESET) == 0) //Maybe?????? (TEST)
{
Log_Info("IF_CTRL HDD Hard Reset");
dev9.ata.ATA_HardReset();
}
if ((regIFCtrl & SPEED_Header.SPD_IF_ATA_RESET) != 0)
{
Log_Info("IF_CTRL ATA Reset");
//0x62 0x0020
regIFCtrl = 0x001A;
//0x66 0x0001
regPIOMode = 0x24;
regMDMAMode = 0x45;
regUDMAMode = 0x83;
//0x74 0x0083
//0x76 0x4ABA (And consequently 0x78 = 0x4ABA.)
}
if ((regIFCtrl & 0xFF00) > 0)
{
Log_Error("IF_CTRL Unkown Bit(s)" + (regIFCtrl & 0xFF00).ToString("X"));
}
#endregion
break;
case SPEED_Header.SPD_R_PIO_MODE: //ATA only? or includes EEPROM?
Log_Verb("SPD_R_PIO_MODE 16bit write " + value.ToString("X"));
regPIOMode = value;
switch (regPIOMode)
{
case 0x92:
Log_Info("SPD_R_PIO_MODE 0");
break;
case 0x72:
Log_Info("SPD_R_PIO_MODE 1");
break;
case 0x32:
Log_Info("SPD_R_PIO_MODE 2");
break;
case 0x24:
Log_Info("SPD_R_PIO_MODE 3");
break;
case 0x23:
Log_Info("SPD_R_PIO_MODE 4");
break;
default:
Log_Error("SPD_R_PIO_MODE UNKOWN MODE " + value.ToString("X"));
break;
}
break;
case SPEED_Header.SPD_R_MWDMA_MODE: //ATA only?
Log_Verb("SPD_R_MDMA_MODE 16bit write " + value.ToString("X"));
regMDMAMode = value;
switch (regMDMAMode)
{
case 0xFF:
Log_Info("SPD_R_MDMA_MODE 0");
break;
case 0x45:
Log_Info("SPD_R_MDMA_MODE 1");
break;
case 0x24:
Log_Info("SPD_R_MDMA_MODE 2");
break;
default:
Log_Error("SPD_R_MDMA_MODE UNKOWN MODE");
break;
}
break;
case SPEED_Header.SPD_R_UDMA_MODE: //ATA only?
Log_Verb("SPD_R_UDMA_MODE 16bit write " + value.ToString("X"));
regUDMAMode = value;
switch (regUDMAMode)
{
case 0xa7:
Log_Info("SPD_R_UDMA_MODE 0");
break;
case 0x85:
Log_Info("SPD_R_UDMA_MODE 1");
break;
case 0x63:
Log_Info("SPD_R_UDMA_MODE 2");
break;
case 0x62:
Log_Info("SPD_R_UDMA_MODE 3");
break;
case 0x61:
Log_Info("SPD_R_UDMA_MODE 4");
break;
default:
Log_Error("SPD_R_UDMA_MODE UNKOWN MODE");
break;
}
break;
default:
dev9.Dev9Wu16((int)addr, value);
Log_Error("*Unknown 16bit write at address " + addr.ToString("X8") + " value " + value.ToString("X"));
return;
}
}