public AOpCodeMemReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Shift = ((OpCode >> 12) & 0x1) != 0;
IntType = (AIntType)((OpCode >> 13) & 0x7);
Rm = (OpCode >> 16) & 0x1f;
Extend64 = ((OpCode >> 22) & 0x3) == 2;
}
public void EmitCast(AIntType IntType)
{
switch (IntType)
{
case AIntType.UInt8: Emit(OpCodes.Conv_U1); break;
case AIntType.UInt16: Emit(OpCodes.Conv_U2); break;
case AIntType.UInt32: Emit(OpCodes.Conv_U4); break;
case AIntType.UInt64: Emit(OpCodes.Conv_U8); break;
case AIntType.Int8: Emit(OpCodes.Conv_I1); break;
case AIntType.Int16: Emit(OpCodes.Conv_I2); break;
case AIntType.Int32: Emit(OpCodes.Conv_I4); break;
case AIntType.Int64: Emit(OpCodes.Conv_I8); break;
}
if (IntType == AIntType.UInt64 ||
IntType == AIntType.Int64)
{
return;
}
if (CurrOp.RegisterSize != ARegisterSize.Int32)
{
Emit(IntType >= AIntType.Int8
? OpCodes.Conv_I8
: OpCodes.Conv_U8);
}
}
public AOpCodeAluRx(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Shift = (OpCode >> 10) & 0x7;
IntType = (AIntType)((OpCode >> 13) & 0x7);
Rm = (OpCode >> 16) & 0x1f;
}
