/// <summary>
/// Analyzes the possible data dependency which might arise from two memory accesses.
/// </summary>
/// <param name="first">some memory access</param>
/// <param name="second">some other memory access</param>
/// <returns>kind of data dependency</returns>
public static EDependencyKind AanalyzeDependency(MemAccessInfo first, MemAccessInfo second)
{
bool overlap = first.Overlaps(second);
if (!overlap)
{
return(EDependencyKind.NoDependency);
}
if (first.Kind == EMemAccessKind.Read && second.Kind == EMemAccessKind.Read)
{
return(EDependencyKind.NoDependency);
}
else if (first.Kind == EMemAccessKind.Write && second.Kind == EMemAccessKind.Write)
{
return(EDependencyKind.WriteAfterWrite);
}
else if (first.Kind == EMemAccessKind.Write)
{
return(EDependencyKind.ReadAfterWrite);
}
else
{
return(EDependencyKind.WriteAfterRead);
}
}
/// <summary>
/// Checks whether a given XIL instruction is a memory access
/// </summary>
/// <param name="i">XIL instruction</param>
/// <param name="mac">memory access information (null if instruction is not a memory access)</param>
/// <returns>whether given XIL instruction is a memory access</returns>
public bool IsMemAccess(XILInstr i, out MemAccessInfo mac)
{
switch (i.Name)
{
case InstructionCodes.RdMemFix:
{
ulong addr = (ulong)i.Operand;
mac = new MemAccessInfo(MemAccessInfo.EMemAccessKind.Read,
addr, addr);
return(true);
}
case InstructionCodes.WrMemFix:
{
ulong addr = (ulong)i.Operand;
mac = new MemAccessInfo(MemAccessInfo.EMemAccessKind.Write,
addr, addr);
return(true);
}
default:
mac = null;
return(false);
}
}
/// <summary>
/// Checks whether this access might refer to the same address as another access
/// </summary>
/// <param name="mac">another memory access</param>
/// <returns>whether both accesses might overlap (i.e. refer to the same memory location)</returns>
public bool Overlaps(MemAccessInfo mac)
{
return(MaxAddress >= mac.MinAddress && mac.MaxAddress >= MinAddress);
}