private static void EmitOps(EmitterContext context, Block block) { for (int opIndex = 0; opIndex < block.OpCodes.Count; opIndex++) { InstOp op = block.OpCodes[opIndex]; if (context.Config.Options.Flags.HasFlag(TranslationFlags.DebugMode)) { string instName; if (op.Emitter != null) { instName = op.Name.ToString(); } else { instName = "???"; context.Config.GpuAccessor.Log($"Invalid instruction at 0x{op.Address:X6} (0x{op.RawOpCode:X16})."); } string dbgComment = $"0x{op.Address:X6}: 0x{op.RawOpCode:X16} {instName}"; context.Add(new CommentNode(dbgComment)); } InstConditional opConditional = new InstConditional(op.RawOpCode); bool noPred = op.Props.HasFlag(InstProps.NoPred); if (!noPred && opConditional.Pred == RegisterConsts.PredicateTrueIndex && opConditional.PredInv) { continue; } Operand predSkipLbl = null; if (Decoder.IsPopBranch(op.Name)) { // If the instruction is a SYNC or BRK instruction with only one // possible target address, then the instruction is basically // just a simple branch, we can generate code similar to branch // instructions, with the condition check on the branch itself. noPred = block.SyncTargets.Count <= 1; } else if (op.Name == InstName.Bra) { noPred = true; } if (!(opConditional.Pred == RegisterConsts.PredicateTrueIndex || noPred)) { Operand label; if (opIndex == block.OpCodes.Count - 1 && block.HasNext()) { label = context.GetLabel(block.Successors[0].Address); } else { label = Label(); predSkipLbl = label; } Operand pred = Register(opConditional.Pred, RegisterType.Predicate); if (opConditional.PredInv) { context.BranchIfTrue(label, pred); } else { context.BranchIfFalse(label, pred); } } context.CurrOp = op; op.Emitter?.Invoke(context); if (predSkipLbl != null) { context.MarkLabel(predSkipLbl); } } }
private static Operation[] DecodeShader( ulong address, IGpuAccessor gpuAccessor, TranslationFlags flags, out ShaderConfig config, out int size, out FeatureFlags featureFlags) { Block[] cfg; if ((flags & TranslationFlags.Compute) != 0) { config = new ShaderConfig(gpuAccessor, flags); cfg = Decoder.Decode(gpuAccessor, address); } else { config = new ShaderConfig(new ShaderHeader(gpuAccessor, address), gpuAccessor, flags); cfg = Decoder.Decode(gpuAccessor, address + HeaderSize); } if (cfg == null) { gpuAccessor.Log("Invalid branch detected, failed to build CFG."); size = 0; featureFlags = FeatureFlags.None; return(Array.Empty <Operation>()); } EmitterContext context = new EmitterContext(config); ulong maxEndAddress = 0; for (int blkIndex = 0; blkIndex < cfg.Length; blkIndex++) { Block block = cfg[blkIndex]; if (maxEndAddress < block.EndAddress) { maxEndAddress = block.EndAddress; } context.CurrBlock = block; context.MarkLabel(context.GetLabel(block.Address)); for (int opIndex = 0; opIndex < block.OpCodes.Count; opIndex++) { OpCode op = block.OpCodes[opIndex]; if ((flags & TranslationFlags.DebugMode) != 0) { string instName; if (op.Emitter != null) { instName = op.Emitter.Method.Name; } else { instName = "???"; gpuAccessor.Log($"Invalid instruction at 0x{op.Address:X6} (0x{op.RawOpCode:X16})."); } string dbgComment = $"0x{op.Address:X6}: 0x{op.RawOpCode:X16} {instName}"; context.Add(new CommentNode(dbgComment)); } if (op.NeverExecute) { continue; } Operand predSkipLbl = null; bool skipPredicateCheck = op is OpCodeBranch opBranch && !opBranch.PushTarget; if (op is OpCodeBranchPop opBranchPop) { // If the instruction is a SYNC or BRK instruction with only one // possible target address, then the instruction is basically // just a simple branch, we can generate code similar to branch // instructions, with the condition check on the branch itself. skipPredicateCheck = opBranchPop.Targets.Count < 2; } if (!(op.Predicate.IsPT || skipPredicateCheck)) { Operand label; if (opIndex == block.OpCodes.Count - 1 && block.Next != null) { label = context.GetLabel(block.Next.Address); } else { label = Label(); predSkipLbl = label; } Operand pred = Register(op.Predicate); if (op.InvertPredicate) { context.BranchIfTrue(label, pred); } else { context.BranchIfFalse(label, pred); } } context.CurrOp = op; op.Emitter?.Invoke(context); if (predSkipLbl != null) { context.MarkLabel(predSkipLbl); } } } size = (int)maxEndAddress + (((flags & TranslationFlags.Compute) != 0) ? 0 : HeaderSize); featureFlags = context.UsedFeatures; return(context.GetOperations()); }
private static void EmitOps(EmitterContext context, Block block) { for (int opIndex = 0; opIndex < block.OpCodes.Count; opIndex++) { OpCode op = block.OpCodes[opIndex]; if ((context.Config.Flags & TranslationFlags.DebugMode) != 0) { string instName; if (op.Emitter != null) { instName = op.Emitter.Method.Name; } else { instName = "???"; context.Config.GpuAccessor.Log($"Invalid instruction at 0x{op.Address:X6} (0x{op.RawOpCode:X16})."); } string dbgComment = $"0x{op.Address:X6}: 0x{op.RawOpCode:X16} {instName}"; context.Add(new CommentNode(dbgComment)); } if (op.NeverExecute) { continue; } Operand predSkipLbl = null; bool skipPredicateCheck = op is OpCodeBranch opBranch && !opBranch.PushTarget; if (op is OpCodeBranchPop opBranchPop) { // If the instruction is a SYNC or BRK instruction with only one // possible target address, then the instruction is basically // just a simple branch, we can generate code similar to branch // instructions, with the condition check on the branch itself. skipPredicateCheck = opBranchPop.Targets.Count < 2; } if (!(op.Predicate.IsPT || skipPredicateCheck)) { Operand label; if (opIndex == block.OpCodes.Count - 1 && block.Next != null) { label = context.GetLabel(block.Next.Address); } else { label = Label(); predSkipLbl = label; } Operand pred = Register(op.Predicate); if (op.InvertPredicate) { context.BranchIfTrue(label, pred); } else { context.BranchIfFalse(label, pred); } } context.CurrOp = op; op.Emitter?.Invoke(context); if (predSkipLbl != null) { context.MarkLabel(predSkipLbl); } } }
private static Operation[] DecodeShader(IGalMemory memory, ulong address, GalShaderType shaderType) { ShaderHeader header = new ShaderHeader(memory, address); Block[] cfg = Decoder.Decode(memory, address); EmitterContext context = new EmitterContext(shaderType, header); for (int blkIndex = 0; blkIndex < cfg.Length; blkIndex++) { Block block = cfg[blkIndex]; context.CurrBlock = block; context.MarkLabel(context.GetLabel(block.Address)); for (int opIndex = 0; opIndex < block.OpCodes.Count; opIndex++) { OpCode op = block.OpCodes[opIndex]; if (op.NeverExecute) { continue; } Operand predSkipLbl = null; bool skipPredicateCheck = op.Emitter == InstEmit.Bra; if (op is OpCodeSync opSync) { //If the instruction is a SYNC instruction with only one //possible target address, then the instruction is basically //just a simple branch, we can generate code similar to branch //instructions, with the condition check on the branch itself. skipPredicateCheck |= opSync.Targets.Count < 2; } if (!(op.Predicate.IsPT || skipPredicateCheck)) { Operand label; if (opIndex == block.OpCodes.Count - 1 && block.Next != null) { label = context.GetLabel(block.Next.Address); } else { label = Label(); predSkipLbl = label; } Operand pred = Register(op.Predicate); if (op.InvertPredicate) { context.BranchIfTrue(label, pred); } else { context.BranchIfFalse(label, pred); } } context.CurrOp = op; op.Emitter(context); if (predSkipLbl != null) { context.MarkLabel(predSkipLbl); } } } return(context.GetOperations()); }