public static void SYSCALL(OpcodeTable.OpcodeDesc Desc) { if (Desc.op4 > 0 && Common.Variables.UTEsyscall) { // Special type of SYSCALL used for the Fraser CPU Tests char TestChar = (char)(Desc.op2 + 64); string TestResult = $"Test Result - Set:{Desc.op3} Test:{Desc.op4} Result:{TestChar}"; if (TestChar == 'F') { Common.Logger.PrintErrorLine(TestResult); } else if (TestChar == 'P') { Common.Logger.PrintSuccessLine(TestResult); } else { Common.Logger.PrintInfoLine(TestResult); } } else { // Regular SYSCALL behavior throw new NotImplementedException("Regular SYSCALL behavior is not implemented."); } Registers.R4300.PC += 4; }
public static void CFC1(OpcodeTable.OpcodeDesc Desc) { if (Desc.op3 == 0 || Desc.op3 == 31) { Registers.R4300.Reg[Desc.op2] = Common.Util.DoubleToUInt64(Registers.COP1.Reg[Desc.op3]) & 0xFFFFFFFF; } else { throw new InvalidOperationException($"CFC1: fs cannot be {Desc.op3}!"); } Registers.R4300.PC += 4; }
public static void CTC1(OpcodeTable.OpcodeDesc Desc) { if (Desc.op3 == 0 || Desc.op3 == 31) { Registers.COP1.Reg[Desc.op3] = Common.Util.UInt64ToDouble((uint)Registers.R4300.Reg[Desc.op2]); } else { throw new InvalidOperationException($"CTC1: fs cannot be {Desc.op3}!"); } Registers.R4300.PC += 4; }
public static void InterpretOpcode(uint Opcode) { if (Registers.R4300.Reg[0] != 0) { Registers.R4300.Reg[0] = 0; } if (Registers.COP0.Reg[Registers.COP0.COUNT_REG] >= 0xFFFFFFFF) { Registers.COP0.Reg[Registers.COP0.COUNT_REG] = 0x0; Count = 0x0; } OpcodeTable.OpcodeDesc Desc = new OpcodeTable.OpcodeDesc(Opcode); OpcodeTable.InstInfo Info = OpcodeTable.GetOpcodeInfo(Opcode); if (Common.Variables.Debug) { string ASM = string.Format( Info.FormattedASM, Desc.op1, Desc.op2, Desc.op3, Desc.op4, Desc.Imm, Desc.Target); Common.Logger.PrintInfoLine($"0x{Registers.R4300.PC:x}: {Convert.ToString(Opcode, 2).PadLeft(32, '0')}: {ASM}"); } Info.Interpret(Desc); CycleCounter += Info.Cycles; Count += Info.Cycles; Registers.COP0.Reg[Registers.COP0.COUNT_REG] = Count >> 1; --Registers.COP0.Reg[Registers.COP0.RANDOM_REG]; if (Registers.COP0.Reg[Registers.COP0.RANDOM_REG] < Registers.COP0.Reg[Registers.COP0.WIRED_REG]) { Registers.COP0.Reg[Registers.COP0.RANDOM_REG] = 0x1F; // TODO: Reset the Random Register to 0x1F after writing to the Wired Register. } Common.Measure.InstructionCount += 1; Common.Measure.CycleCounter = CycleCounter; }
public static void BREAK(OpcodeTable.OpcodeDesc Desc) { Common.Util.Cleanup(Registers.R4300.PC); throw new Common.Exceptions.ProgramBreakPointException("Guest broke execution."); }
public static void LB(OpcodeTable.OpcodeDesc Desc) { Registers.R4300.Reg[Desc.op2] = (ulong)Memory.ReadInt8((ulong)(Desc.op1 + Desc.Imm)); }