public RiscVDisassembler(RiscVArchitecture arch, EndianImageReader rdr) { this.arch = arch; this.rdr = rdr; this.addrInstr = rdr.Address; this.state = new State(); }
public RiscVRewriter(RiscVArchitecture arch, ImageReader rdr, ProcessorState state, Frame frame, IRewriterHost host) { this.arch = arch; this.dasm = new RiscVDisassembler(arch, rdr).GetEnumerator(); this.state = state; this.frame = frame; this.host = host; }
public RiscVRewriter(RiscVArchitecture arch, EndianImageReader rdr, ProcessorState state, IStorageBinder binder, IRewriterHost host) { this.arch = arch; this.dasm = new RiscVDisassembler(arch, rdr).GetEnumerator(); this.state = state; this.binder = binder; this.host = host; }
public RiscVRewriter(RiscVArchitecture arch, Decoder[] decoders, EndianImageReader rdr, ProcessorState state, IStorageBinder binder, IRewriterHost host) { this.arch = arch; this.dasm = new RiscVDisassembler(arch, decoders, rdr).GetEnumerator(); this.state = state; this.binder = binder; this.host = host; this.rdr = rdr; this.rtlInstructions = new List <RtlInstruction>(); this.m = new RtlEmitter(rtlInstructions); this.instr = default !;
public RiscVDisassembler(RiscVArchitecture arch, EndianImageReader rdr) { this.arch = arch; this.rdr = rdr; }
public RiscVState(RiscVArchitecture arch) { this.arch = arch; }
public RiscVState(RiscVState that) : base(that) { this.arch = that.arch; this.InstructionPointer = that.InstructionPointer; }
public RiscVState(RiscVArchitecture arch) { this.arch = arch; }
public RiscVState(RiscVState that) : base(that) { this.arch = that.arch; this.pc = that.pc; }