public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to cycles when uops are executed on port 0 // anyThread sometimes works (i7-4712HQ) and sometimes not (E5-1620v3). It works on SNB. // don't set anythread for consistent behavior ulong retiredBranches = GetPerfEvtSelRegisterValue(0xA1, 0x01, usr: true, os: true, edge: false, pc: false, interrupt: false, anyThread: false, enable: true, invert: false, cmask: 0); Ring0.WriteMsr(IA32_PERFEVTSEL0, retiredBranches); // Set PMC1 to count ^ for port 1 ulong retiredMispredictedBranches = GetPerfEvtSelRegisterValue(0xA1, 0x02, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL1, retiredMispredictedBranches); // Set PMC2 to count ^ for port 5 ulong branchResteers = GetPerfEvtSelRegisterValue(0xA1, 0x20, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL2, branchResteers); // Set PMC3 to count ^ for port 6 ulong notTakenBranches = GetPerfEvtSelRegisterValue(0xA1, 0x40, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL3, notTakenBranches); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xD0, 0x81, true, true, false, false, false, false, true, false, cmask: 0)); // all loads Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xD0, 0x41, true, true, false, false, false, false, true, false, cmask: 0)); // locked loads Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xF4, 0x10, true, true, false, false, false, false, true, false, cmask: 0)); // SQ split locks Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xD2, 0x4, true, true, false, false, false, false, true, false, cmask: 0)); // Snoop hit } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xA3, 0x4, true, true, false, false, false, false, true, false, cmask: 4)); // no execute Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xA3, 0x6, true, true, false, false, false, false, true, false, cmask: 6)); // L3 miss pending stall Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xA3, 0xC, true, true, false, false, false, false, true, false, cmask: 0xC)); // L1D pending, pmc2 only Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xA3, 0x5, true, true, false, false, false, false, true, false, cmask: 5)); // L2 Pending } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // scalar single Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xC7, 0x2, true, true, false, false, false, false, true, false, cmask: 0)); // scalar 128B packed Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xC7, 0x8, true, true, false, false, false, false, true, false, cmask: 0)); // scalar 256B packed Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xC7, 0x20, true, true, false, false, false, false, true, false, cmask: 0)); // All FP instr retired Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xC7, 0xFF, true, true, false, false, false, false, true, false, cmask: 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // PMC0: IFTAG_HIT Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x83, 0x1, true, true, false, false, false, false, true, false, 0)); // PMC1: IFTAG_MISS Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x83, 0x2, true, true, false, false, false, false, true, false, 0)); // PMC2: ITLB Miss, STLB Hit Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x85, 0x20, true, true, false, false, false, false, true, false, 0)); // PMC3: STLB miss, page walk Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x85, 0x1, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // PMC0: walk pending cycles, load Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x08, 0x10, true, true, false, false, false, false, true, false, 1)); // PMC1: 2 walk pending cycles, load Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x08, 0x10, true, true, false, false, false, false, true, false, 2)); // PMC2: 3 walk pending cycles, load Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x08, 0x10, true, true, false, false, false, false, true, false, 3)); // PMC3: ROB Full (undoc) Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x80, 0x10, true, true, false, false, false, false, true, false, 4)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // PMC0: All dispatch stalls Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xA2, 0x1, true, true, false, false, false, false, true, false, 0)); // PMC1: SB Full Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xA2, 0x8, true, true, false, false, false, false, true, false, 0)); // PMC1: RS Full (undoc) Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xA2, 0x4, true, true, false, false, false, false, true, false, 0)); // PMC3: ROB Full (undoc) Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xA2, 0x10, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // cmask 4 Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x60, 0x8, true, true, false, false, false, false, true, false, cmask: 4)); // cmask 8 Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x60, 0x8, true, true, false, false, false, false, true, false, cmask: 8)); // cmask 12 Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x60, 0x8, true, true, false, false, false, false, true, false, cmask: 16)); // cmask 16 Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x60, 0x8, true, true, false, false, false, false, true, false, cmask: 33)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // PMC0: All loads retired (kind of like AMD DC Access) Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xD0, 0x81, true, true, false, false, false, false, true, false, 0)); // PMC1: L2 hit (kind of like AMD refill from L2) Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xD1, 0x2, true, true, false, false, false, false, true, false, 0)); // PMC1: L3 hit Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xD1, 0x4, true, true, false, false, false, false, true, false, 0)); // PMC3: L3 miss Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xD1, 0x20, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to count l2 references Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x24, 0xFF, true, true, false, false, false, false, true, false, 0)); // Set PMC1 to count l2 misses Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x24, 0x3F, true, true, false, false, false, false, true, false, 0)); // Set PMC2 to count L2 lines in Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xF1, 0x1F, true, true, false, false, false, false, true, false, 0)); // Set PMC3 to count dirty L2 lines evicted Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xF2, 0x2, true, true, false, false, false, false, true, false, 0)); } }