public static void TraceInclusionCheck(ConfigurationBase currentImpl, Automata spec, VerificationOutput VerificationOutput) { FAState[] states = spec.States.Values.ToArray(); //bool[] isFinal = new bool[states.Length]; bool[,] fsim = new bool[states.Length, states.Length]; // sim[u][v]=true iff v in sim(u) iff v simulates u //for (int i = 0; i < states.Length; i++) //{ // isFinal[i] = spec.F.Contains(states[i]); //} for (int i = 0; i < states.Length; i++) { for (int j = i; j < states.Length; j++) { fsim[i, j] = states[j].covers(states[i]); //(!isFinal[i] || isFinal[j]) && fsim[j, i] = states[i].covers(states[j]); //(isFinal[i] || !isFinal[j]) && } } Dictionary <string, HashSet <FAState> > rel_spec = FastFSimRelNBW(spec, fsim); StringHashTable Visited = new StringHashTable(Ultility.Ultility.MC_INITIAL_SIZE); List <ConfigurationBase> toReturn = new List <ConfigurationBase>(); Stack <ConfigurationBase> pendingImpl = new Stack <ConfigurationBase>(1024); Stack <NormalizedFAState> pendingSpec = new Stack <NormalizedFAState>(1024); //The following are for identifying a counterexample trace. Stack <int> depthStack = new Stack <int>(1024); depthStack.Push(0); List <int> depthList = new List <int>(1024); //The above are for identifying a counterexample trace. //implementation initial state pendingImpl.Push(currentImpl); //specification initial state NormalizedFAState currentSpec = new NormalizedFAState(spec.InitialState, rel_spec); #if TEST pendingSpec.Push(currentSpec.TauReachable()); #else pendingSpec.Push(currentSpec); #endif while (pendingImpl.Count > 0) { currentImpl = pendingImpl.Pop(); currentSpec = pendingSpec.Pop(); string ID = currentImpl.GetID() + Constants.SEPARATOR + currentSpec.GetID(); if (Visited.ContainsKey(ID)) { continue; } Visited.Add(ID); //The following are for identifying a counterexample trace. int depth = depthStack.Pop(); while (depth > 0 && depthList[depthList.Count - 1] >= depth) { int lastIndex = depthList.Count - 1; depthList.RemoveAt(lastIndex); toReturn.RemoveAt(lastIndex); } toReturn.Add(currentImpl); depthList.Add(depth); //If the specification has no corresponding state, then it implies that the trace is allowed by the //implementation but not the specification -- which means trace-refinement is failed. if (currentSpec.States.Count == 0) { VerificationOutput.NoOfStates = Visited.Count; VerificationOutput.CounterExampleTrace = toReturn; VerificationOutput.VerificationResult = VerificationResultType.INVALID; return; } ConfigurationBase[] nextImpl = currentImpl.MakeOneMove(); VerificationOutput.Transitions += nextImpl.Length; for (int k = 0; k < nextImpl.Length; k++) { ConfigurationBase next = nextImpl[k]; if (next.Event != Constants.TAU) { NormalizedFAState nextSpec = currentSpec.Next(next.Event, rel_spec); pendingImpl.Push(next); pendingSpec.Push(nextSpec); depthStack.Push(depth + 1); } else { pendingImpl.Push(next); pendingSpec.Push(currentSpec); depthStack.Push(depth + 1); } } } VerificationOutput.NoOfStates = Visited.Count; VerificationOutput.VerificationResult = VerificationResultType.VALID; //return null; }