public void Write(ushort address, byte data)
{
if (address == 0x7EF0)
{
Map.Switch2kChrRom(((data >> 1) & 0x3F) * 2, 0);
}
else if (address == 0x7EF1)
{
Map.Switch2kChrRom(((data >> 1) & 0x3F) * 2, 1);
}
else if (address == 0x7EF2)
{
Map.Switch1kChrRom(data, 4);
}
else if (address == 0x7EF3)
{
Map.Switch1kChrRom(data, 5);
}
else if (address == 0x7EF4)
{
Map.Switch1kChrRom(data, 6);
}
else if (address == 0x7EF5)
{
Map.Switch1kChrRom(data, 7);
}
else if (address == 0x7EF6)
{
if ((address & 0x1) == 0)
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
else
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
Map.ApplayMirroring();
}
else if (address == 0x7EF8)
{
//if (data == 0xA3)
// Map.IsSRAMReadOnly = true;
//else if (data == 0xFF)
// Map.IsSRAMReadOnly = false;
}
else if (address == 0x7EFA)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else if (address == 0x7EFC)
{
Map.Switch8kPrgRom(data * 2, 1);
}
else if (address == 0x7EFE)
{
Map.Switch8kPrgRom(data * 2, 2);
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
case 0x42FE:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
if ((data & 0x10) != 0)
{
Map.Cartridge.MirroringBase = 0x2400;
}
else
{
Map.Cartridge.MirroringBase = 0x2000;
}
Map.ApplayMirroring();
break;
case 0x42FF:
if ((data & 0x10) != 0)
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
Map.ApplayMirroring();
break;
case 0x4501: IRQEnabled = false; break;
case 0x4502: irq_counter = (short)((irq_counter & 0xFF00) | data); break;
case 0x4503: irq_counter = (short)((data << 8) | (irq_counter & 0x00FF)); IRQEnabled = true; break;
case 0x4504:
case 0x4505:
case 0x4506:
case 0x4507: Map.Switch8kPrgRom(data * 2, address & 0x03); break;
case 0x4510:
case 0x4511:
case 0x4512:
case 0x4513:
case 0x4514:
case 0x4515:
case 0x4516:
case 0x4517: Map.Switch1kChrRom(data, address & 0x07); break;
}
}
void SetCHR()
{
if (mapper4_chrAddressSelect == 0)
{
_Map.Switch2kChrRom(chr0, 0);
_Map.Switch2kChrRom(chr1, 1);
_Map.Switch1kChrRom(chr2, 4);
_Map.Switch1kChrRom(chr3, 5);
_Map.Switch1kChrRom(chr4, 6);
_Map.Switch1kChrRom(chr5, 7);
}
else
{
_Map.Switch2kChrRom(chr0, 2);
_Map.Switch2kChrRom(chr1, 3);
_Map.Switch1kChrRom(chr2, 0);
_Map.Switch1kChrRom(chr3, 1);
_Map.Switch1kChrRom(chr4, 2);
_Map.Switch1kChrRom(chr5, 3);
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
case 0x9FFF: Map.Cartridge.Mirroring = ((data & 0x01) == 0) ? Mirroring.Vertical : Mirroring.Horizontal;
mapper32SwitchingMode = ((data & 0x02) == 0) ? 0 : 1;
Map.ApplayMirroring();
break;
case 0x8FFF:
if (mapper32SwitchingMode == 0)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else
{
Map.Switch8kPrgRom(data * 2, 2);
}
break;
case 0xAFFF: Map.Switch8kPrgRom(data * 2, 1); break;
case 0xBFF0: Map.Switch1kChrRom(data, 0); break;
case 0xBFF1: Map.Switch1kChrRom(data, 1); break;
case 0xBFF2: Map.Switch1kChrRom(data, 2); break;
case 0xBFF3: Map.Switch1kChrRom(data, 3); break;
case 0xBFF4: Map.Switch1kChrRom(data, 4); break;
case 0xBFF5: Map.Switch1kChrRom(data, 5); break;
case 0xBFF6: Map.Switch1kChrRom(data, 6); break;
case 0xBFF7: Map.Switch1kChrRom(data, 7); break;
}
}
void SetCHR()
{
int[] bank = new int[8];
for (int i = 0; i < 8; i++)
{
bank[i] = (chh_reg[i] << 8) | (chl_reg[i]);
}
if (chr_size == 0)
{
mem.Switch8kChrRom(bank[0] * 8);
}
else if (chr_size == 1)
{
mem.Switch4kChrRom(bank[0] * 4, 0);
mem.Switch4kChrRom(bank[4] * 4, 1);
}
else if (chr_size == 2)
{
mem.Switch2kChrRom(bank[0] * 2, 0);
mem.Switch2kChrRom(bank[2] * 2, 1);
mem.Switch2kChrRom(bank[4] * 2, 2);
mem.Switch2kChrRom(bank[6] * 2, 3);
}
else
{
mem.Switch1kChrRom(bank[0], 0);
mem.Switch1kChrRom(bank[1], 1);
mem.Switch1kChrRom(bank[2], 2);
mem.Switch1kChrRom(bank[3], 3);
mem.Switch1kChrRom(bank[4], 4);
mem.Switch1kChrRom(bank[5], 5);
mem.Switch1kChrRom(bank[6], 6);
mem.Switch1kChrRom(bank[7], 7);
}
}
public void Write(ushort address, byte data)
{
if (address == 0x8000)
{
Map.Switch8kPrgRom((data & 0x1F) * 2, 0);
if (type1)
{
if ((data & 0x40) == 0x40)
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
Map.ApplayMirroring();
}
}
else if (address == 0x8001)
{
Map.Switch8kPrgRom(data * 2, 1);
}
else if (address == 0x8002)
{
Map.Switch2kChrRom(data * 2, 0);
}
else if (address == 0x8003)
{
Map.Switch2kChrRom(data * 2, 1);
}
else if (address == 0xA000)
{
Map.Switch1kChrRom(data, 4);
}
else if (address == 0xA001)
{
Map.Switch1kChrRom(data, 5);
}
else if (address == 0xA002)
{
Map.Switch1kChrRom(data, 6);
}
else if (address == 0xA003)
{
Map.Switch1kChrRom(data, 7);
}
//Type 2 registers
else if (address == 0xC000)
{
type1 = false;
IRQCounter = data;
}
else if (address == 0xC001)
{
type1 = false;
IRQCounter = data;
}
else if (address == 0xC002)
{
type1 = false;
IRQEabled = true;
}
else if (address == 0xC003)
{
type1 = false;
IRQEabled = false;
}
else if (address == 0xE000)
{
type1 = false;
if ((data & 0x40) == 0x40)
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
Map.ApplayMirroring();
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
/*PRG*/
case 0x8000: _Map.Switch8kPrgRom(data * 2, 0); break;
case 0x8010:
case 0x8008: _Map.Switch8kPrgRom(data * 2, 1); break;
case 0x9000: _Map.Switch8kPrgRom(data * 2, 2); break;
/*CHR*/
case 0xA000: _Map.Switch1kChrRom(data, 0); break;
case 0xA008:
case 0xA010: _Map.Switch1kChrRom(data, 1); break;
case 0xB000: _Map.Switch1kChrRom(data, 2); break;
case 0xB008:
case 0xB010: _Map.Switch1kChrRom(data, 3); break;
case 0xC000: _Map.Switch1kChrRom(data, 4); break;
case 0xC008:
case 0xC010: _Map.Switch1kChrRom(data, 5); break;
case 0xD000: _Map.Switch1kChrRom(data, 6); break;
case 0xD008:
case 0xD010: _Map.Switch1kChrRom(data, 7); break;
/*Mirroring*/
case 0xE000:
data &= 0x03;
if (data == 0)
{
_Map.Cartridge.Mirroring = Mirroring.Vertical;
}
else if (data == 1)
{
_Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else if (data == 2)
{
_Map.Cartridge.Mirroring = Mirroring.One_Screen;
_Map.Cartridge.MirroringBase = 0x2000;
}
else
{
_Map.Cartridge.Mirroring = Mirroring.One_Screen;
_Map.Cartridge.MirroringBase = 0x2400;
}
_Map.ApplayMirroring();
break;
case 0xE008:
case 0xE010:
irq_latch = data;
break;
case 0xF000:
irq_enable = data & 0x03;
irq_counter = irq_latch;
irq_clock = 0;
break;
case 0xF008:
case 0xF010:
irq_enable = (irq_enable & 0x01) * 3;
break;
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
case 0x8000: Map.Switch16kPrgRom(data * 4, 0); break;
case 0xB003:
switch (data & 0x3)
{
case 0: Map.Cartridge.Mirroring = Mirroring.Vertical; break;
case 1: Map.Cartridge.Mirroring = Mirroring.Horizontal; break;
case 2:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2000;
break;
case 3:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2400;
break;
}
Map.ApplayMirroring();
break;
case 0xC000: Map.Switch8kPrgRom(data * 2, 2); break;
case 0xD000: Map.Switch1kChrRom(data, 0); break;
case 0xD001: Map.Switch1kChrRom(data, 1); break;
case 0xD002: Map.Switch1kChrRom(data, 2); break;
case 0xD003: Map.Switch1kChrRom(data, 3); break;
case 0xE000: Map.Switch1kChrRom(data, 4); break;
case 0xE001: Map.Switch1kChrRom(data, 5); break;
case 0xE002: Map.Switch1kChrRom(data, 6); break;
case 0xE003: Map.Switch1kChrRom(data, 7); break;
case 0xF000:
irq_latch = data;
break;
case 0xF001:
irq_enable = (data & 0x01) != 0;
break;
case 0xF002:
irq_counter = irq_latch;
break;
//Sound
//Pulse 1
case 0x9000:
Map.apu.VRC6PULSE1.Write9000(data);
break;
case 0x9001:
Map.apu.VRC6PULSE1.Write9001(data);
break;
case 0x9002:
Map.apu.VRC6PULSE1.Write9002(data);
break;
//Pulse 2
case 0xA000:
Map.apu.VRC6PULSE2.WriteA000(data);
break;
case 0xA001:
Map.apu.VRC6PULSE2.WriteA001(data);
break;
case 0xA002:
Map.apu.VRC6PULSE2.WriteA002(data);
break;
//Sawtooth
case 0xB000:
Map.apu.VRC6SAWTOOTH.WriteB000(data);
break;
case 0xB001:
Map.apu.VRC6SAWTOOTH.WriteB001(data);
break;
case 0xB002:
Map.apu.VRC6SAWTOOTH.WriteB002(data);
break;
}
}
void SetBank_PPU()
{
if ((reg & 0x80) != 0)
{
//SetVROM_8K_Bank( chr4, chr5, chr6, chr7,
// chr01, chr01+1, chr23, chr23+1 );
Map.Switch1kChrRom(chr4, 0);
Map.Switch1kChrRom(chr5, 1);
Map.Switch1kChrRom(chr6, 2);
Map.Switch1kChrRom(chr7, 3);
Map.Switch1kChrRom(chr01, 4);
Map.Switch1kChrRom(chr01 + 1, 5);
Map.Switch1kChrRom(chr23, 6);
Map.Switch1kChrRom(chr23 + 1, 7);
}
else
{
//SetVROM_8K_Bank( chr01, chr01+1, chr23, chr23+1,
// chr4, chr5, chr6, chr7 );
Map.Switch1kChrRom(chr01, 0);
Map.Switch1kChrRom(chr01 + 1, 1);
Map.Switch1kChrRom(chr23, 2);
Map.Switch1kChrRom(chr23 + 1, 3);
Map.Switch1kChrRom(chr4, 4);
Map.Switch1kChrRom(chr5, 5);
Map.Switch1kChrRom(chr6, 6);
Map.Switch1kChrRom(chr7, 7);
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
/*Swap mode*/
case 0x9001:
case 0x9004:
SwapMode = (data & 0X2) == 0X2;
break;
/*prg selection 1*/
case 0x8000:
case 0x8002:
case 0x8004:
case 0x8006:
if (!SwapMode)
{
_Map.Switch16kPrgRom((_Map.Cartridge.PRG_PAGES - 1) * 4, 1);
_Map.Switch8kPrgRom((data & 0X1f) * 2, 0);
}
else
{
_Map.Switch16kPrgRom((_Map.Cartridge.PRG_PAGES - 1) * 4, 1);
_Map.Switch8kPrgRom((data & 0X1f) * 2, 2);
}
break;
/*prg selection 2*/
case 0xA000:
case 0xA002:
case 0xA004:
case 0xA006:
_Map.Switch8kPrgRom((data & 0X1f) * 2, 1);
break;
/*Mirroring Control*/
case 0x9000:
case 0x9002:
data &= 0x03;
if (data == 0)
{
_Map.Cartridge.Mirroring = Mirroring.Vertical;
}
else if (data == 1)
{
_Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else if (data == 2)
{
_Map.Cartridge.Mirroring = Mirroring.One_Screen;
_Map.Cartridge.MirroringBase = 0x2000;
}
else
{
_Map.Cartridge.Mirroring = Mirroring.One_Screen;
_Map.Cartridge.MirroringBase = 0x2400;
}
_Map.ApplayMirroring();
break;
/*CHR Selection*/
case 0xB000:
reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[0], 0);
break;
case 0xB002:
case 0xB008:
reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[0], 0);
break;
case 0xB001:
case 0xB004:
reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[1], 1);
break;
case 0xB003:
case 0xB00C:
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[1], 1);
break;
case 0xC000:
reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[2], 2);
break;
case 0xC002:
case 0xC008:
reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[2], 2);
break;
case 0xC001:
case 0xC004:
reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[3], 3);
break;
case 0xC003:
case 0xC00C:
reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[3], 3);
break;
case 0xD000:
reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[4], 4);
break;
case 0xD002:
case 0xD008:
reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[4], 4);
break;
case 0xD001:
case 0xD004:
reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[5], 5);
break;
case 0xD003:
case 0xD00C:
reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[5], 5);
break;
case 0xE000:
reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[6], 6);
break;
case 0xE002:
case 0xE008:
reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[6], 6);
break;
case 0xE001:
case 0xE004:
reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F));
_Map.Switch1kChrRom(reg[7], 7);
break;
case 0xE003:
case 0xE00C:
reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4));
_Map.Switch1kChrRom(reg[7], 7);
break;
/*IRQs*/
case 0xF000:
irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
break;
case 0xF002:
case 0xF008:
irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
break;
case 0xF001:
case 0xF004:
irq_enable = (byte)(data & 0x03);
irq_counter = irq_latch;
irq_clock = 0;
break;
case 0xF003:
case 0xF00C:
irq_enable = (byte)((irq_enable & 0x01) * 3);
break;
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
case 0x8000:
reg[0] = (reg[0] & 0xF0) | (data & 0x0F);
Map.Switch8kPrgRom(reg[0] * 2, 0);
break;
case 0x8001:
reg[0] = (reg[0] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch8kPrgRom(reg[0] * 2, 0);
break;
case 0x8002:
reg[1] = (reg[1] & 0xF0) | (data & 0x0F);
Map.Switch8kPrgRom(reg[1] * 2, 1);
break;
case 0x8003:
reg[1] = (reg[1] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch8kPrgRom(reg[1] * 2, 1);
break;
case 0x9000:
reg[2] = (reg[2] & 0xF0) | (data & 0x0F);
Map.Switch8kPrgRom(reg[2] * 2, 2);
break;
case 0x9001:
reg[2] = (reg[2] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch8kPrgRom(reg[2] * 2, 2);
break;
case 0xA000:
reg[3] = (reg[3] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[3], 0);
break;
case 0xA001:
reg[3] = (reg[3] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[3], 0);
break;
case 0xA002:
reg[4] = (reg[4] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[4], 1);
break;
case 0xA003:
reg[4] = (reg[4] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[4], 1);
break;
case 0xB000:
reg[5] = (reg[5] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[5], 2);
break;
case 0xB001:
reg[5] = (reg[5] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[5], 2);
break;
case 0xB002:
reg[6] = (reg[6] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[6], 3);
break;
case 0xB003:
reg[6] = (reg[6] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[6], 3);
break;
case 0xC000:
reg[7] = (reg[7] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[7], 4);
break;
case 0xC001:
reg[7] = (reg[7] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[7], 4);
break;
case 0xC002:
reg[8] = (reg[8] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[8], 5);
break;
case 0xC003:
reg[8] = (reg[8] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[8], 5);
break;
case 0xD000:
reg[9] = (reg[9] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[9], 6);
break;
case 0xD001:
reg[9] = (reg[9] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[9], 6);
break;
case 0xD002:
reg[10] = (reg[10] & 0xF0) | (data & 0x0F);
Map.Switch1kChrRom(reg[10], 7);
break;
case 0xD003:
reg[10] = (reg[10] & 0x0F) | ((data & 0x0F) << 4);
Map.Switch1kChrRom(reg[10], 7);
break;
case 0xE000:
irq_latch = (irq_latch & 0xFFF0) | (data & 0x0F);
break;
case 0xE001:
irq_latch = (irq_latch & 0xFF0F) | ((data & 0x0F) << 4);
break;
case 0xE002:
irq_latch = (irq_latch & 0xF0FF) | ((data & 0x0F) << 8);
break;
case 0xE003:
irq_latch = (irq_latch & 0x0FFF) | ((data & 0x0F) << 12);
break;
case 0xF000:
irq_counter = irq_latch;
break;
case 0xF001:
irq_mode = (data >> 1) & 0x07;
irq_enable = (data & 0x01);
break;
case 0xF002:
data &= 0x03;
if (data == 0)
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else if (data == 1)
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
else
{
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2000;
}
Map.ApplayMirroring();
break;
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
case 0x8000:
if (!PRGMode)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else
{
Map.Switch8kPrgRom(data * 2, 2);
}
break;
case 0xA000:
Map.Switch8kPrgRom(data * 2, 1);
break;
case 0x9000:
switch (data & 0x3)
{
case 0: Map.Cartridge.Mirroring = Mirroring.Vertical; break;
case 1: Map.Cartridge.Mirroring = Mirroring.Horizontal; break;
case 2:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2000;
break;
case 3:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2400;
break;
}
Map.ApplayMirroring();
break;
case 0x9080:
case 0x9002:
PRGMode = (data & 0x2) == 0x2;
break;
case 0xB000:
REG[0] = (byte)((REG[0] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[0], 0);
break;
case 0xB002:
case 0xB040:
REG[0] = (byte)(((data & 0x0F) << 4) | (REG[0] & 0x0F));
Map.Switch1kChrRom(REG[0], 0);
break;
case 0xB001:
case 0xB004:
case 0xB080:
REG[1] = (byte)((REG[1] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[1], 1);
break;
case 0xB003:
case 0xB006:
case 0xB0C0:
REG[1] = (byte)(((data & 0x0F) << 4) | (REG[1] & 0x0F));
Map.Switch1kChrRom(REG[1], 1);
break;
case 0xC000:
REG[2] = (byte)((REG[2] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[2], 2);
break;
case 0xC002:
case 0xC040:
REG[2] = (byte)(((data & 0x0F) << 4) | (REG[2] & 0x0F));
Map.Switch1kChrRom(REG[2], 2);
break;
case 0xC001:
case 0xC004:
case 0xC080:
REG[3] = (byte)((REG[3] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[3], 3);
break;
case 0xC003:
case 0xC006:
case 0xC0C0:
REG[3] = (byte)(((data & 0x0F) << 4) | (REG[3] & 0x0F));
Map.Switch1kChrRom(REG[3], 3);
break;
case 0xD000:
REG[4] = (byte)((REG[4] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[4], 4);
break;
case 0xD002:
case 0xD040:
REG[4] = (byte)(((data & 0x0F) << 4) | (REG[4] & 0x0F));
Map.Switch1kChrRom(REG[4], 4);
break;
case 0xD001:
case 0xD004:
case 0xD080:
REG[5] = (byte)((REG[5] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[5], 5);
break;
case 0xD003:
case 0xD006:
case 0xD0C0:
REG[5] = (byte)(((data & 0x0F) << 4) | (REG[5] & 0x0F));
Map.Switch1kChrRom(REG[5], 5);
break;
case 0xE000:
REG[6] = (byte)((REG[6] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[6], 6);
break;
case 0xE002:
case 0xE040:
REG[6] = (byte)(((data & 0x0F) << 4) | (REG[6] & 0x0F));
Map.Switch1kChrRom(REG[6], 6);
break;
case 0xE001:
case 0xE004:
case 0xE080:
REG[7] = (byte)((REG[7] & 0xF0) | (data & 0x0F));
Map.Switch1kChrRom(REG[7], 7);
break;
case 0xE003:
case 0xE006:
case 0xE0C0:
REG[7] = (byte)(((data & 0x0F) << 4) | (REG[7] & 0x0F));
Map.Switch1kChrRom(REG[7], 7);
break;
case 0xF000:
irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
break;
case 0xF002:
case 0xF040:
irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
break;
case 0xF003:
case 0xF0C0:
case 0xF006:
irq_enable = (irq_enable & 0x01) * 3;
irq_clock = 0;
break;
case 0xF004:
case 0xF080:
irq_enable = data & 0x03;
if ((irq_enable & 0x02) != 0)
{
irq_counter = irq_latch;
irq_clock = 0;
}
break;
}
}
public void Write(ushort address, byte data)
{
switch (address & 0xE000)
{
case 0x8000:
reg = data;
break;
case 0xA000:
switch (reg & 0x0F)
{
case 0x00: Map.Switch1kChrRom(data, 0); break;
case 0x01: Map.Switch1kChrRom(data, 1); break;
case 0x02: Map.Switch1kChrRom(data, 2); break;
case 0x03: Map.Switch1kChrRom(data, 3); break;
case 0x04: Map.Switch1kChrRom(data, 4); break;
case 0x05: Map.Switch1kChrRom(data, 5); break;
case 0x06: Map.Switch1kChrRom(data, 6); break;
case 0x07: Map.Switch1kChrRom(data, 7); break;
case 0x08:
if ((data & 0x40) == 0)
{
Map.Switch8kPrgRomToSRAM((data & 0x3F) * 2);
}
break;
case 0x09:
Map.Switch8kPrgRom(data * 2, 0);
break;
case 0x0A:
Map.Switch8kPrgRom(data * 2, 1);
break;
case 0x0B:
Map.Switch8kPrgRom(data * 2, 2);
break;
case 0x0C:
data &= 0x03;
if (data == 0)
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
if (data == 1)
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
if (data == 2)
{
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2000;
}
if (data == 3)
{
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2400;
}
Map.ApplayMirroring();
break;
case 0x0D:
if (data == 0)
{
timer_irq_enabled = false;
}
if (data == 0x81)
{
timer_irq_enabled = true;
}
break;
case 0x0E:
timer_irq_counter_69 = (short)((timer_irq_counter_69 & 0xFF00) | data);
break;
case 0x0F:
timer_irq_counter_69 = (short)((timer_irq_counter_69 & 0x00FF) | (data << 8));
break;
}
break;
case 0xC000:
case 0xE000:
break;
}
}
public void Write(ushort address, byte data)
{
switch (address & 0xF)
{
case 0: Map.Switch1kChrRom(data, 0); break;
case 1: Map.Switch1kChrRom(data, 1); break;
case 2: Map.Switch1kChrRom(data, 2); break;
case 3: Map.Switch1kChrRom(data, 3); break;
case 4: Map.Switch1kChrRom(data, 4); break;
case 5: Map.Switch1kChrRom(data, 5); break;
case 6: Map.Switch1kChrRom(data, 6); break;
case 7: Map.Switch1kChrRom(data, 7); break;
case 8: Map.Switch16kPrgRom(data * 4, 0); break;
case 9: switch (data & 0x3)
{
case 0:
Map.Cartridge.Mirroring = Mirroring.Vertical;
break;
case 1:
Map.Cartridge.Mirroring = Mirroring.Horizontal;
break;
case 2:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2000;
break;
case 3:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2400;
break;
}
Map.ApplayMirroring();
break;
case 0xA:
timer_irq_enabled = ((data & 0x1) != 0);
timer_irq_counter_16 = timer_irq_Latch_16;
break;
case 0xB:
timer_irq_Latch_16 = (short)((timer_irq_Latch_16 & 0xFF00) | data);
break;
case 0xC:
timer_irq_Latch_16 = (short)((data << 8) | (timer_irq_Latch_16 & 0x00FF));
break;
case 0xD: break; //
}
}
public void Write(ushort address, byte data)
{
if (address == 0x7EF0)
{
if (Swapped)
{
Map.Switch2kChrRom((data >> 1) * 2, 2);
}
else
{
Map.Switch2kChrRom((data >> 1) * 2, 0);
}
}
else if (address == 0x7EF1)
{
if (Swapped)
{
Map.Switch2kChrRom((data >> 1) * 2, 3);
}
else
{
Map.Switch2kChrRom((data >> 1) * 2, 1);
}
}
else if (address == 0x7EF2)
{
if (Swapped)
{
Map.Switch1kChrRom(data, 0);
}
else
{
Map.Switch1kChrRom(data, 4);
}
}
else if (address == 0x7EF3)
{
if (Swapped)
{
Map.Switch1kChrRom(data, 1);
}
else
{
Map.Switch1kChrRom(data, 5);
}
}
else if (address == 0x7EF4)
{
if (Swapped)
{
Map.Switch1kChrRom(data, 2);
}
else
{
Map.Switch1kChrRom(data, 6);
}
}
else if (address == 0x7EF5)
{
if (Swapped)
{
Map.Switch1kChrRom(data, 3);
}
else
{
Map.Switch1kChrRom(data, 7);
}
}
else if (address == 0x7EF6)
{
Swapped = ((data & 0x2) >> 1) != 0;
if ((data & 0x01) == 0)
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
Map.ApplayMirroring();
}
else if (address == 0x7EFA)
{
Map.Switch8kPrgRom((data >> 2) * 2, 0);
}
else if (address == 0x7EFB)
{
Map.Switch8kPrgRom((data >> 2) * 2, 1);
}
else if (address == 0x7EFC)
{
Map.Switch8kPrgRom((data >> 2) * 2, 2);
}
}
void SetCHR()
{
//if (patch)
//{
// SetVROM_8K_Bank(chr01, chr01 + 1, chr23, chr23 + 1,
// chr4, chr5, chr6, chr7);
//}
//else
// {
if (mem.Cartridge.IsVRAM)
{
if ((reg[0] & 0x80) != 0)
{
//SetVROM_8K_Bank(chr4, chr5, chr6, chr7,
// chr01, chr01 + 1, chr23, chr23 + 1);
mem.Switch1kChrRom(chr4, 0);
mem.Switch1kChrRom(chr5, 1);
mem.Switch1kChrRom(chr6, 2);
mem.Switch1kChrRom(chr7, 3);
mem.Switch1kChrRom(chr01, 4);
mem.Switch1kChrRom(chr01 + 1, 5);
mem.Switch1kChrRom(chr23, 6);
mem.Switch1kChrRom(chr23 + 1, 7);
}
else
{
//SetVROM_8K_Bank(chr01, chr01 + 1, chr23, chr23 + 1,
// chr4, chr5, chr6, chr7);
mem.Switch1kChrRom(chr01, 0);
mem.Switch1kChrRom(chr01 + 1, 1);
mem.Switch1kChrRom(chr23, 2);
mem.Switch1kChrRom(chr23 + 1, 3);
mem.Switch1kChrRom(chr4, 4);
mem.Switch1kChrRom(chr5 + 1, 5);
mem.Switch1kChrRom(chr6, 6);
mem.Switch1kChrRom(chr7 + 1, 7);
}
}
else
{
if ((reg[0] & 0x80) != 0)
{
mem.Switch1kChrRom((chr01 + 0) & 0x07, 4);
mem.Switch1kChrRom((chr01 + 1) & 0x07, 5);
mem.Switch1kChrRom((chr23 + 0) & 0x07, 6);
mem.Switch1kChrRom((chr23 + 1) & 0x07, 7);
mem.Switch1kChrRom(chr4 & 0x07, 0);
mem.Switch1kChrRom(chr5 & 0x07, 1);
mem.Switch1kChrRom(chr6 & 0x07, 2);
mem.Switch1kChrRom(chr7 & 0x07, 3);
}
else
{
mem.Switch1kChrRom((chr01 + 0) & 0x07, 0);
mem.Switch1kChrRom((chr01 + 1) & 0x07, 1);
mem.Switch1kChrRom((chr23 + 0) & 0x07, 2);
mem.Switch1kChrRom((chr23 + 1) & 0x07, 3);
mem.Switch1kChrRom(chr4 & 0x07, 4);
mem.Switch1kChrRom(chr5 & 0x07, 5);
mem.Switch1kChrRom(chr6 & 0x07, 6);
mem.Switch1kChrRom(chr7 & 0x07, 7);
}
}
// }
}
public void Write(ushort address, byte data)
{
if (address == 0x8000)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else if (address == 0x9000)
{
switch (data & 0x3)
{
case 0: Map.Cartridge.Mirroring = Mirroring.Vertical; break;
case 1: Map.Cartridge.Mirroring = Mirroring.Horizontal; break;
case 2:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2400;
break;
case 3:
Map.Cartridge.Mirroring = Mirroring.One_Screen;
Map.Cartridge.MirroringBase = 0x2000;
break;
}
Map.ApplayMirroring();
}
else if (address == 0xA000)
{
Map.Switch8kPrgRom(data * 2, 1);
}
else if (address == 0xB000)
{
Map.Switch1kChrRom((data >> 1), 0);
}
else if (address == 0xB001)
{
Map.Switch1kChrRom((data >> 1), 1);
}
else if (address == 0xC000)
{
Map.Switch1kChrRom((data >> 1), 2);
}
else if (address == 0xC001)
{
Map.Switch1kChrRom((data >> 1), 3);
}
else if (address == 0xD000)
{
Map.Switch1kChrRom((data >> 1), 4);
}
else if (address == 0xD001)
{
Map.Switch1kChrRom((data >> 1), 5);
}
else if (address == 0xE000)
{
Map.Switch1kChrRom((data >> 1), 6);
}
else if (address == 0xE001)
{
Map.Switch1kChrRom((data >> 1), 7);
}
}
public void Write(ushort address, byte data)
{
if (address == 0x8000)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else if (address == 0xA000)
{
Map.Switch8kPrgRom(data * 2, 1);
}
else if (address == 0xC000)
{
Map.Switch8kPrgRom(data * 2, 2);
}
else if (address == 0x9003)
{
timer_irq_enabled = ((data & 0x80) != 0);
}
else if (address == 0x9004)
{
timer_irq_counter_65 = timer_irq_Latch_65;
}
else if (address == 0x9005)
{
timer_irq_Latch_65 = (short)((timer_irq_Latch_65 & 0x00FF) | (data << 8));
}
else if (address == 0x9006)
{
timer_irq_Latch_65 = (short)((timer_irq_Latch_65 & 0xFF00) | (data));
}
else if (address == 0xB000)
{
Map.Switch1kChrRom(data, 0);
}
else if (address == 0xB001)
{
Map.Switch1kChrRom(data, 1);
}
else if (address == 0xB002)
{
Map.Switch1kChrRom(data, 2);
}
else if (address == 0xB003)
{
Map.Switch1kChrRom(data, 3);
}
else if (address == 0xB004)
{
Map.Switch1kChrRom(data, 4);
}
else if (address == 0xB005)
{
Map.Switch1kChrRom(data, 5);
}
else if (address == 0xB006)
{
Map.Switch1kChrRom(data, 6);
}
else if (address == 0xB007)
{
Map.Switch1kChrRom(data, 7);
}
}
void SetCHR()
{
if ((reg[2] & 0x02) != 0)
{
MEM.Switch1kChrRom(chr01, 0);
MEM.Switch1kChrRom(chr01 + 1, 1);
MEM.Switch1kChrRom(chr23, 2);
MEM.Switch1kChrRom(chr23 + 1, 3);
MEM.Switch1kChrRom(chr4, 4);
MEM.Switch1kChrRom(chr5, 5);
MEM.Switch1kChrRom(chr6, 6);
MEM.Switch1kChrRom(chr7, 7);
}
else
{
MEM.Switch1kChrRom(((reg[3] << 6) & 0x100) + chr01, 0);
MEM.Switch1kChrRom(((reg[3] << 6) & 0x100) + chr01 + 1, 1);
MEM.Switch1kChrRom(((reg[3] << 5) & 0x100) + chr23, 2);
MEM.Switch1kChrRom(((reg[3] << 5) & 0x100) + chr23 + 1, 3);
MEM.Switch1kChrRom(((reg[3] << 4) & 0x100) + chr4, 4);
MEM.Switch1kChrRom(((reg[3] << 3) & 0x100) + chr5, 5);
MEM.Switch1kChrRom(((reg[3] << 2) & 0x100) + chr6, 6);
MEM.Switch1kChrRom(((reg[3] << 1) & 0x100) + chr7, 7);
}
}
public void Write(ushort address, byte data)
{
if (address == 0x8000)
{
mapper64_commandNumber = data;
mapper64_prgAddressSelect = (byte)(data & 0x40);
mapper64_chrAddressSelect = (byte)(data & 0x80);
}
else if (address == 0x8001)
{
if ((mapper64_commandNumber & 0xf) == 0)
{
//Swap 2 1k chr roms
data = (byte)(data - (data % 2));
if (mapper64_chrAddressSelect == 0)
{
Map.Switch2kChrRom(data, 0);
}
else
{
Map.Switch2kChrRom(data, 2);
}
}
else if ((mapper64_commandNumber & 0xf) == 1)
{
//Swap 2 1k chr roms
data = (byte)(data - (data % 2));
if (mapper64_chrAddressSelect == 0)
{
Map.Switch2kChrRom(data, 1);
}
else
{
Map.Switch2kChrRom(data, 3);
}
}
else if ((mapper64_commandNumber & 0xf) == 2)
{
//Swap 1k chr rom
if (mapper64_chrAddressSelect == 0)
{
Map.Switch1kChrRom(data, 4);
}
else
{
Map.Switch1kChrRom(data, 0);
}
}
else if ((mapper64_commandNumber & 0xf) == 3)
{
//Swap 1k chr rom
if (mapper64_chrAddressSelect == 0)
{
Map.Switch1kChrRom(data, 5);
}
else
{
Map.Switch1kChrRom(data, 1);
}
}
else if ((mapper64_commandNumber & 0xf) == 4)
{
//Swap 1k chr rom
if (mapper64_chrAddressSelect == 0)
{
Map.Switch1kChrRom(data, 6);
}
else
{
Map.Switch1kChrRom(data, 2);
}
}
else if ((mapper64_commandNumber & 0xf) == 5)
{
//Swap 1k chr rom
if (mapper64_chrAddressSelect == 0)
{
Map.Switch1kChrRom(data, 7);
}
else
{
Map.Switch1kChrRom(data, 3);
}
}
else if ((mapper64_commandNumber & 0xf) == 6)
{
if (mapper64_prgAddressSelect == 0)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else
{
Map.Switch8kPrgRom(data * 2, 1);
}
}
else if ((mapper64_commandNumber & 0xf) == 7)
{
if (mapper64_prgAddressSelect == 0)
{
Map.Switch8kPrgRom(data * 2, 1);
}
else
{
Map.Switch8kPrgRom(data * 2, 2);
}
}
else if ((mapper64_commandNumber & 0xf) == 8)
{
Map.Switch1kChrRom(data, 1);
}
else if ((mapper64_commandNumber & 0xf) == 9)
{
Map.Switch1kChrRom(data, 3);
}
else if ((mapper64_commandNumber & 0xf) == 0xf)
{
if (mapper64_prgAddressSelect == 0)
{
Map.Switch8kPrgRom(data * 2, 2);
}
else
{
Map.Switch8kPrgRom(data * 2, 0);
}
}
}
else if (address == 0xA000)
{
if ((data & 1) == 1)
{
Map.Cartridge.Mirroring = Mirroring.Vertical;
}
else
{
Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
Map.ApplayMirroring();
}
}
public void Write(ushort address, byte data)
{
/*IRQ controls*/
if (address >= 0x5000 & address <= 0x57FF)
{
irq_counter = (short)((irq_counter & 0xFF00) | data);
}
else if (address >= 0x5800 & address <= 0x5FFF)
{
IRQEnabled = (data & 0x80) != 0;
irq_counter = (short)((irq_counter & 0x00FF) | (data & 0x7F) << 8);
}
/*Pattern Table Control*/
else if (address >= 0x8000 & address <= 0x87FF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 0);
}
else
{
Map.Switch1kCRAM(data, 0);
}
}
else if (address >= 0x8800 & address <= 0x8FFF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 1);
}
else
{
Map.Switch1kCRAM(data, 1);
}
}
else if (address >= 0x9000 & address <= 0x97FF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 2);
}
else
{
Map.Switch1kCRAM(data, 2);
}
}
else if (address >= 0x9800 & address <= 0x9FFF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 3);
}
else
{
Map.Switch1kCRAM(data, 3);
}
}
else if (address >= 0xA000 & address <= 0xA7FF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 4);
}
else
{
Map.Switch1kCRAM(data, 4);
}
}
else if (address >= 0xA800 & address <= 0xAFFF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 5);
}
else
{
Map.Switch1kCRAM(data, 5);
}
}
else if (address >= 0xB000 & address <= 0xB7FF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 6);
}
else
{
Map.Switch1kCRAM(data, 6);
}
}
else if (address >= 0xB800 & address <= 0xBFFF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 7);
}
else
{
Map.Switch1kCRAM(data, 7);
}
}
/*Name Table Control*/
else if (address >= 0xC000 & address <= 0xC7FF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 0);
}
else
{
Map.SwitchVRAMToVRAM(data, 0);
}
}
else if (address >= 0xC800 & address <= 0xCFFF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 1);
}
else
{
Map.SwitchVRAMToVRAM(data, 1);
}
}
else if (address >= 0xD000 & address <= 0xD7FF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 2);
}
else
{
Map.SwitchVRAMToVRAM(data, 2);
}
}
else if (address >= 0xD800 & address <= 0xDFFF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 3);
}
else
{
Map.SwitchVRAMToVRAM(data, 3);
}
}
/*CPU Memory Control*/
else if (address >= 0xE000 & address <= 0xE7FF)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else if (address >= 0xE800 & address <= 0xEFFF)
{
if (address == 0xE800)
{
VROMRAMfor0000 = (data & 0x40) == 0x40;
VROMRAMfor1000 = (data & 0x80) == 0x80;
}
Map.Switch8kPrgRom(data * 2, 1);
}
else if (address >= 0xF000 & address <= 0xF7FF)
{
Map.Switch8kPrgRom(data * 2, 2);
}
}
public void Write(ushort address, byte data)
{
switch (address)
{
case 0x8000:
//case 0x8003:
_Map.Switch16kPrgRom(data * 4, 0);
break;
case 0xC000:
//case 0xC003:
_Map.Switch8kPrgRom(data * 2, 2);
break;
case 0xB003:
int mm = data & 0x7F;
if (mm == 0x20)
{
_Map.Cartridge.Mirroring = Mirroring.Vertical;
}
else if (mm == 0x24)
{
_Map.Cartridge.Mirroring = Mirroring.Horizontal;
}
else if (mm == 0x28)
{
_Map.Cartridge.Mirroring = Mirroring.One_Screen;
_Map.Cartridge.MirroringBase = 0x2000;
}
else if (mm == 0x08 || mm == 0x2C)
{
_Map.Cartridge.Mirroring = Mirroring.One_Screen;
_Map.Cartridge.MirroringBase = 0x2400;
}
_Map.ApplayMirroring();
break;
case 0xD000: _Map.Switch1kChrRom(data, 0); break;
case 0xD001: _Map.Switch1kChrRom(data, 2); break;
case 0xD002: _Map.Switch1kChrRom(data, 1); break;
case 0xD003: _Map.Switch1kChrRom(data, 3); break;
case 0xE000: _Map.Switch1kChrRom(data, 4); break;
case 0xE001: _Map.Switch1kChrRom(data, 6); break;
case 0xE002: _Map.Switch1kChrRom(data, 5); break;
case 0xE003: _Map.Switch1kChrRom(data, 7); break;
case 0xF000:
irq_latch = data;
break;
case 0xF001:
irq_enable = (irq_enable & 0x01) * 3;
break;
case 0xF002:
irq_enable = data & 0x03;
if ((irq_enable & 0x02) != 0)
{
irq_counter = irq_latch;
irq_clock = 0;
}
break;
//Sound
//Pulse 1
case 0x9000:
_Map.apu.VRC6PULSE1.Write9000(data);
break;
case 0x9001:
_Map.apu.VRC6PULSE1.Write9001(data);
break;
case 0x9002:
_Map.apu.VRC6PULSE1.Write9002(data);
break;
//Pulse 2
case 0xA000:
_Map.apu.VRC6PULSE2.WriteA000(data);
break;
case 0xA001:
_Map.apu.VRC6PULSE2.WriteA001(data);
break;
case 0xA002:
_Map.apu.VRC6PULSE2.WriteA002(data);
break;
//Sawtooth
case 0xB000:
_Map.apu.VRC6SAWTOOTH.WriteB000(data);
break;
case 0xB001:
_Map.apu.VRC6SAWTOOTH.WriteB001(data);
break;
case 0xB002:
_Map.apu.VRC6SAWTOOTH.WriteB002(data);
break;
}
}
