//constructor
public MemCtrl(uint rmax, DDR3DRAM ddr3)
{
this.cid = cmax;
cmax++;
//states
this.rmax = rmax;
this.bmax = ddr3.BANK_MAX;
//DDR3
timing = ddr3.timing;
this.col_max = ddr3.COL_MAX;
this.row_size = ddr3.COL_MAX * ddr3.CHANNEL_WIDTH;
//components
chan = new Channel(this, rmax, ddr3.BANK_MAX);
//row-hit finder
rh_finder = new RowHitFinder(this);
//queues
int readq_max = Config.mctrl.readq_max_per_bank;
writeq_max = (int)this.rmax * (int)this.bmax * Config.mctrl.writeq_max_per_bank;
readqs = new List <Req> [rmax, bmax];
writeqs = new List <Req> [rmax, bmax];
mctrl_writeq = new List <Req>(writeq_max);
inflightqs = new List <Req> [rmax, bmax];
cmdqs = new List <Cmd> [rmax, bmax];
for (uint r = 0; r < rmax; r++)
{
for (uint b = 0; b < bmax; b++)
{
readqs[r, b] = new List <Req>(readq_max);
writeqs[r, b] = new List <Req>(writeq_max);
inflightqs[r, b] = new List <Req>(INFLIGHTQ_MAX);
cmdqs[r, b] = new List <Cmd>(CMDQ_MAX);
}
}
bus_q = new List <BusTransaction>((int)BUS_TRANSACTIONS_MAX);
//stats
rload_per_proc = new uint[Config.N];
rload_per_procrankbank = new uint[Config.N, rmax, bmax];
shadow_rowid_per_procrankbank = new ulong[Config.N, rmax, bmax];
rowid_per_procrankbank = new ulong[rmax, bmax];
pid_rowid_per_procrankbank = new int[rmax, bmax];
wload_per_proc = new uint[Config.N];
wload_per_procrankbank = new uint[Config.N, rmax, bmax];
//writeback throttler
wbthrottle = Activator.CreateInstance(Config.sched.typeof_wbthrottle_algo) as WBThrottle;
total_queueing_latency = new ulong[Config.N];
curr_proc = new int[bmax];
}
public static void UpdateDict(Dictionary <ulong, AccessInfo> dict, Req req, MemCtrl mctrl)
{//Need to update NVM dictionary when a request comes out of L2
//Need to update both dictionary when a request
AccessInfo temp;
if (!dict.ContainsKey(KeyGen(req)))
{//If dictionary does not have this record
temp.ReadMiss = 0;
temp.WriteMiss = 0;
temp.ReadHit = 0;
temp.WriteHit = 0;
temp.Access = 1;
temp.ReadMLPnum = 1;
temp.WriteMLPnum = 1;
temp.ReadMLPAcc = 0;
temp.ReadMLPTimes = 0;
temp.WriteMLPAcc = 0;
temp.WriteMLPTimes = 0;
temp.pid = req.pid;
temp.addlist = false;
//not in the dictionary means a cold miss
if (req.type == ReqType.RD)
{
temp.ReadMiss++;
}
else
{
temp.WriteMiss++;
}
dict.Add(KeyGen(req), temp);
NVMLookUp.Add(KeyGen(req));
}
else
{//If dictionary has this record
temp = dict[KeyGen(req)];
temp.Access++;
RowHitFinder rhf = new RowHitFinder(mctrl);
if (rhf.is_row_hit(req)) // a hit
{
if (req.type == ReqType.RD)
{
temp.ReadHit++;
}
else
{
temp.WriteHit++;
}
}
else
{
if (req.type == ReqType.RD)
{
temp.ReadMiss++;
}
else
{
temp.WriteMiss++;
}
}
dict[KeyGen(req)] = temp;
}
RowCache.NVMCache.insert(KeyGen(req));
}
//constructor
public MemCtrl(uint rmax, DDR3DRAM ddr3)
{
this.cid = cmax;
cmax++;
//states
this.rmax = rmax;
this.bmax = ddr3.BANK_MAX;
//DDR3
timing = ddr3.timing;
this.col_max = ddr3.COL_MAX;
this.row_size = ddr3.COL_MAX * ddr3.CHANNEL_WIDTH;
//components
chan = new Channel(this, rmax, ddr3.BANK_MAX);
//row-hit finder
rh_finder = new RowHitFinder(this);
//queues
int readq_max = Config.mctrl.readq_max_per_bank;
writeq_max = (int)this.rmax * (int)this.bmax * Config.mctrl.writeq_max_per_bank;
readqs = new List<Req>[rmax, bmax];
writeqs = new List<Req>[rmax, bmax];
mctrl_writeq = new List<Req>(writeq_max);
inflightqs = new List<Req>[rmax, bmax];
cmdqs = new List<Cmd>[rmax, bmax];
for (uint r = 0; r < rmax; r++) {
for (uint b = 0; b < bmax; b++) {
readqs[r, b] = new List<Req>(readq_max);
writeqs[r, b] = new List<Req>(writeq_max);
inflightqs[r, b] = new List<Req>(INFLIGHTQ_MAX);
cmdqs[r, b] = new List<Cmd>(CMDQ_MAX);
}
}
bus_q = new List<BusTransaction>((int)BUS_TRANSACTIONS_MAX);
//stats
rload_per_proc = new uint[Config.N];
rload_per_procrankbank = new uint[Config.N, rmax, bmax];
shadow_rowid_per_procrankbank = new ulong[Config.N, rmax, bmax];
rowid_per_procrankbank = new ulong[rmax, bmax];
pid_rowid_per_procrankbank = new int[rmax, bmax];
wload_per_proc = new uint[Config.N];
wload_per_procrankbank = new uint[Config.N, rmax, bmax];
//writeback throttler
wbthrottle = Activator.CreateInstance(Config.sched.typeof_wbthrottle_algo) as WBThrottle;
total_queueing_latency = new ulong[Config.N];
curr_proc = new int[bmax];
}