public void issue_insts(bool issued_rd_req)
{
//issue instructions
for (int i = 0; i < Config.proc.ipc; i++)
{
if (inst_wnd.is_full())
{
if (i == 0)
{
Stat.procs[pid].stall_inst_wnd.Collect();
// Measurement.core_stall_cycles[pid] += 1;
}
return;
}
//cpu instructions
if (curr_cpu_inst_cnt > 0)
{
curr_cpu_inst_cnt--;
inst_wnd.add(0, false, true);
continue;
}
//only one memory instruction can be issued per cycle
if (issued_rd_req)
{
return;
}
//memory instruction (only AFTER checking for one memory instruction per cycle)
inst_wnd.add(curr_rd_req.block_addr, true, false);
//check if true miss
bool false_miss = inst_wnd.is_duplicate(curr_rd_req.block_addr);
if (false_miss)
{
Dbg.Assert(curr_rd_req.wb_req == null);
RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
continue;
}
//try mshr
bool mshr_ok = insert_mshr(curr_rd_req);
if (!mshr_ok)
{
mshr_retry = true;
return;
}
//try memory controller
bool mctrl_ok = insert_mctrl(curr_rd_req);
if (!mctrl_ok)
{
mctrl_retry = true;
return;
}
//issued memory request
issued_rd_req = true;
//get new read request
curr_rd_req = get_req();
}
}
public void issue_insts(bool issued_rd_req)
{
//issue instructions
for (int i = 0; i < Config.proc.ipc; i++)
{
if (inst_wnd.is_full())
{
if (i == 0)
{
Stat.procs[pid].stall_inst_wnd.Collect();
}
return;
}
//cpu instructions
if (curr_cpu_inst_cnt > 0)
{
curr_cpu_inst_cnt--;
inst_wnd.add(0, false, true, 0);
continue;
}
//only one memory instruction can be issued per cycle
if (issued_rd_req)
{
return;
}
//check if true miss
bool false_miss = inst_wnd.is_duplicate(curr_rd_req.block_addr);
if (false_miss)
{
bool get_ready = inst_wnd.get_ready_status(curr_rd_req.block_addr);
bool get_alone_hit = inst_wnd.get_alone_hit_status(curr_rd_req.block_addr);
inst_wnd.add(curr_rd_req.block_addr, true, get_ready, get_alone_hit, curr_rd_req.pc);
Dbg.Assert(curr_rd_req.wb_req == null);
RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
continue;
}
if (!Config.is_cache_filtered)
{
bool is_in_l1_cache = false;
is_in_l1_cache = l1_cache.has_addr(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
if (is_in_l1_cache)
{
if (pid == Sim.highest_rank_proc)
{
Sim.cache_controller.count_l1_hits(pid, true);
}
Sim.cache_controller.count_l1_hits(pid, false);
Stat.procs[pid].l1_cache_hit_count.Collect();
inst_wnd.add(curr_rd_req.block_addr, true, true, true, curr_rd_req.pc);
RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
continue;
}
bool mshr_ok = insert_mshr(curr_rd_req);
if (!mshr_ok)
{
mshr_retry = true;
return;
}
Stat.procs[pid].l1_cache_miss_count.Collect();
if (pid == Sim.highest_rank_proc)
{
Sim.cache_controller.count_l1_misses(pid, true);
}
Sim.cache_controller.count_l1_misses(pid, false);
}
is_in_cache = false;
is_alone_hit = false;
if (!Config.is_cache_filtered)
{
int way_sampled_set = cache.has_addr_sampled_set(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
is_in_cache = cache.has_addr(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
//Count high-priority and non-high-priority hits and misses in the sampled sets
if (!is_in_cache)
{
Sim.cache_controller.count_misses(pid, way_sampled_set, false);
}
if (!is_in_cache && (pid == Sim.highest_rank_proc))
{
Sim.cache_controller.count_misses(pid, way_sampled_set, true);
}
if (is_in_cache && (pid == Sim.highest_rank_proc))
{
Sim.cache_controller.count_current_hits(pid, way_sampled_set, true);
}
if (is_in_cache)
{
Sim.cache_controller.count_current_hits(pid, way_sampled_set, false);
}
//Count high-priority and non-high-priority hits and misses in all sets
if (!is_in_cache)
{
Sim.cache_controller.count_all_misses(pid, false);
}
if (!is_in_cache && (pid == Sim.highest_rank_proc))
{
Sim.cache_controller.count_all_misses(pid, true);
}
if (is_in_cache && (pid == Sim.highest_rank_proc))
{
Sim.cache_controller.count_all_hits(pid, true);
}
if (is_in_cache)
{
Sim.cache_controller.count_all_hits(pid, false);
}
if (Config.aux_cache)
{
way_sampled_set = aux_cache.has_addr_sampled_set(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
is_alone_hit = aux_cache.has_addr(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
//count aux tag store hits in sampled sets
if (pid == Sim.highest_rank_proc)
{
Sim.cache_controller.count_aux_hits_alone(pid, way_sampled_set);
}
Sim.cache_controller.count_aux_hits(pid, way_sampled_set);
}
if (Config.fst)
{
if (Config.poll_filter)
{
is_alone_hit = pollution_vector.check_filter(curr_rd_req.block_addr);
}
else if (Config.aux_cache)
{
is_alone_hit = aux_cache.has_addr(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
}
}
}
if (Config.fst)
{
if (is_alone_hit)
{
curr_rd_req.alone_counter_tracker = (int)Config.mem_latency;
setting_counter++;
interference_bit = true;
if (Config.poll_filter)
{
interference_bit_core = pollution_vector.get_interfering_core(curr_rd_req.block_addr);
}
interference_bit_set_addr = curr_rd_req.block_addr;
}
}
if (is_alone_hit)
{
curr_rd_req.is_alone_hit = true;
}
// if (Config.stride_prefetcher_on) stride_prefetcher.process_request(pid, curr_rd_req.block_addr, curr_rd_req.pc);
//check if already in cache
if (!Config.is_cache_filtered)
{
if (is_in_cache)
{
Stat.procs[pid].l2_cache_hit_count.Collect();
add_to_cache_queue(curr_rd_req);
// RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
continue;
}
}
if (Config.stride_prefetcher_on)
{
stride_prefetcher.process_request(pid, curr_rd_req.block_addr, curr_rd_req.pc);
}
inst_wnd.add(curr_rd_req.block_addr, true, false, curr_rd_req.is_alone_hit, curr_rd_req.pc);
if (Config.model_memory)
{
//try memory controller
bool mctrl_ok = insert_mctrl(curr_rd_req);
if (!mctrl_ok)
{
mctrl_retry = true;
return;
}
}
else
{
add_to_mem_queue(curr_rd_req);
}
Stat.procs[pid].l2_cache_miss_count.Collect();
//issued memory request
issued_rd_req = true;
//get new read request
curr_rd_req = get_req();
}
}
public void issue_insts(bool issued_rd_req)
{
//issue instructions
for (int i = 0; i < Config.proc.ipc; i++)
{
if (inst_wnd.is_full())
{
if (i == 0)
{
Stat.procs[pid].stall_inst_wnd.Collect();
}
return;
}
// Console.Write(" i - " + i + " Proc IPC - " + Config.proc.ipc + "\n");
//cpu instructions
if (curr_cpu_inst_cnt > 0)
{
curr_cpu_inst_cnt--;
inst_wnd.add(0, false, true, 0);
continue;
}
//only one memory instruction can be issued per cycle
if (issued_rd_req)
{
return;
}
//check if true miss
bool false_miss = inst_wnd.is_duplicate(curr_rd_req.block_addr);
if (false_miss)
{
Dbg.Assert(curr_rd_req.wb_req == null);
RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
continue;
}
if (!Config.is_cache_filtered)
{
bool is_in_l1_cache = false;
is_in_l1_cache = l1_cache.has_addr(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
if (is_in_l1_cache)
{
Stat.procs[pid].l1_cache_hit_count.Collect();
RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
inst_wnd.add(curr_rd_req.block_addr, true, true, curr_rd_req.pc);
continue;
}
Stat.procs[pid].l1_cache_miss_count.Collect();
}
is_in_cache = false;
is_cache_hit = false;
if (!Config.is_cache_filtered)
{
is_in_cache = cache.has_addr(curr_rd_req.block_addr, curr_rd_req.proc_req_type);
}
//check if already in cache
if (!Config.is_cache_filtered)
{
if (is_in_cache)
{
Stat.procs[pid].l2_cache_hit_count.Collect();
add_to_cache_queue(curr_rd_req);
curr_rd_req = get_req();
continue;
}
}
inst_wnd.add(curr_rd_req.block_addr, true, false, false, curr_rd_req.pc);
if (Config.model_memory)
{
//try mshr
bool mshr_ok = insert_mshr(curr_rd_req);
if (!mshr_ok)
{
mshr_retry = true;
return;
}
//try memory controller
bool mctrl_ok = insert_mctrl(curr_rd_req);
if (!mctrl_ok)
{
mctrl_retry = true;
return;
}
}
else
{
add_to_mem_queue(curr_rd_req);
}
Stat.procs[pid].l2_cache_miss_count.Collect();
misses++;
//issued memory request
issued_rd_req = true;
//get new read request
curr_rd_req = get_req();
}
}