private bool can_write(MemAddr addr)
{
Dbg.Assert(bus_q.Count < bus_q.Capacity);
BusTransaction trans = new BusTransaction(addr, cycles + (timing.tCWL + timing.tBL));
if (bus_q.Count > 0)
{
BusTransaction last_trans = bus_q[bus_q.Count - 1];
return(chan.can_write(addr.rid, addr.bid) && (trans.ts - last_trans.ts >= timing.tBL));
}
return(chan.can_write(addr.rid, addr.bid));
}
private void write(MemAddr addr, int pid)
{
chan.write(addr.rid, addr.bid);
Dbg.Assert(bus_q.Count < bus_q.Capacity);
BusTransaction trans = new BusTransaction(addr, cycles + (timing.tCWL + timing.tBL), pid);
//check for bus conflict
if (bus_q.Count > 0)
{
BusTransaction last_trans = bus_q[bus_q.Count - 1];
Dbg.Assert(trans.ts - last_trans.ts >= timing.tBL);
}
bus_q.Add(trans);
}
new public void CheckBusConflict()
{
if (bus_q.Count == 0)
{
return;
}
BusTransaction last_trans = bus_q[bus_q.Count - 1];
MemAddr addr = last_trans.addr;
for (int i = 0; i < rmax; i++)
{
for (int j = 0; j < bmax; j++)
{
if (cmdqs[i, j].Count == 0)
{
continue;
}
if (inflightqs[i, j][0].pid == inflightqs[addr.rid, addr.bid][0].pid)
{
continue;
}
if (cmdqs[i, j][0].type == Cmd.TypeEnum.READ)
{
if (cycles + (timing.tCL + timing.tBL) - last_trans.ts < timing.tBL)
{
if (chan.can_read((uint)i, (uint)j))
{
Measurement.Dram_bus_conflict_set(cmdqs[i, j][0].pid);
}
}
}
else if (cmdqs[i, j][0].type == Cmd.TypeEnum.WRITE)
{
if (cycles + (timing.tCWL + timing.tBL) - last_trans.ts < timing.tBL)
{
if (chan.can_write((uint)i, (uint)j))
{
Measurement.Dram_bus_conflict_set(cmdqs[i, j][0].pid);
}
}
}
}
}
}
private void write(MemAddr addr, int pid)
{
chan.write(addr.rid, addr.bid);
Dbg.Assert(bus_q.Count < bus_q.Capacity);
BusTransaction trans = new BusTransaction(addr, cycles + (timing.tCWL + timing.tBL), pid);
//check for bus conflict
if (bus_q.Count > 0) {
BusTransaction last_trans = bus_q[bus_q.Count - 1];
Dbg.Assert(trans.ts - last_trans.ts >= timing.tBL);
}
bus_q.Add(trans);
}
