public bool doStep()
{
if (m_trace == null)
{
return(true);
}
int syncID;
ulong retired =
(ulong)m_ins.retire(Config.proc.instructionsPerCycle);
if (retired > 0)
{
m_last_retired = Simulator.CurrentRound;
}
if (!m_trace_valid)
{
m_trace_valid = advanceTrace(); // doStats needs to see the next record
}
doStats(retired);
if (m_ins.isFull())
{
return(true);
}
bool done = false;
int nIns = Config.proc.instructionsPerCycle;
int nMem = 1;
while (!done && nIns > 0 && !m_ins.isFull())
{
if (!m_trace_valid)
{
m_trace_valid = advanceTrace();
}
if (!m_trace_valid)
{
return(false);
}
if (m_trace.type == Trace.Type.Pause) // when execution-driven, source has nothing to give
{
m_trace_valid = false;
return(true);
}
if (m_trace.type == Trace.Type.Sync)
{
// `from' field: translate referrent from thd ID to physical CPU id
syncID = Simulator.network.workload.mapThd(m_group, m_trace.from);
}
else
{
syncID = m_trace.from;
}
switch (m_trace.type)
{
case Trace.Type.Rd:
case Trace.Type.Wr:
if (nMem == 0 || !canIssueMSHR(m_trace.address))
{
done = true;
break;
}
nMem--;
nIns--;
ulong addr = m_trace.address;
bool isWrite = m_trace.type == Trace.Type.Wr;
bool inWindow = m_ins.contains(addr, isWrite);
Request req = inWindow ? null : new Request(m_ID, addr, isWrite);
m_ins.fetch(req, addr, isWrite, inWindow);
if (!inWindow)
{
issueReq(req);
}
m_trace_valid = false;
break;
case Trace.Type.NonMem:
if (m_trace.address > 0)
{
m_ins.fetch(null, InstructionWindow.NULL_ADDRESS, false, true);
m_trace.address--;
nIns--;
}
else
{
m_trace_valid = false;
}
break;
case Trace.Type.Label:
if (m_sync.Label(m_ID, syncID, m_trace.address))
{
m_trace_valid = false; // allowed to continue
}
else
{ // shouldn't ever block...
if (m_stats_active)
{
Simulator.stats.cpu_sync_memdep[m_ID].Add();
}
done = true; // blocking: done with this cycle
}
break;
case Trace.Type.Sync:
if (m_sync.Sync(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{
if (m_stats_active)
{
Simulator.stats.cpu_sync_memdep[m_ID].Add();
}
done = true;
}
break;
case Trace.Type.Lock:
//Console.WriteLine("Lock" + ' ' + m_ID.ToString() + ' ' + syncID.ToString() + ' ' + m_trace.address.ToString());
if (m_sync.Lock(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{
if (m_stats_active)
{
Simulator.stats.cpu_sync_lock[m_ID].Add();
}
done = true;
}
break;
case Trace.Type.Unlock:
//Console.WriteLine("Unlock" + ' ' + m_ID.ToString() + ' ' + syncID.ToString() + ' ' + m_trace.address.ToString());
if (m_sync.Unlock(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{ // shouldn't ever block...
if (m_stats_active)
{
Simulator.stats.cpu_sync_lock[m_ID].Add();
}
done = true;
}
break;
case Trace.Type.Barrier:
//Console.WriteLine("Barrier" + ' ' + m_ID.ToString() + ' ' + syncID.ToString() + ' ' + m_trace.address.ToString());
if (m_sync.Barrier(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{
if (m_stats_active)
{
Simulator.stats.cpu_sync_barrier[m_ID].Add();
}
done = true;
}
break;
}
}
return(true);
}
public bool doStep()
{
if (m_trace == null)
{
return(true);
}
/* HWA CODE */
// if( !Simulator.QoSCtrl.is_initialized )
// Simulator.QoSCtrl.schedule_quantum();
if (m_is_GPU)
{
m_MemoryCoalescing.doStep();
}
int syncID;
// Console.WriteLine("core:{1} step: cyc {0}", Simulator.CurrentRound, m_ID);
ulong retired;
if (m_is_GPU)
{
retired = (ulong)m_ins.retire(Config.proc.GPUinstructionsPerCycle);
}
else
{
retired = (ulong)m_ins.retire(Config.proc.instructionsPerCycle);
}
/* HWA CODE */
if (m_is_HWA)
{
deadLineReqCnt += retired;
}
/* HWA_CODE END */
if (retired > 0)
{
m_last_retired = Simulator.CurrentRound;
}
if (!m_trace_valid)
{
m_trace_valid = advanceTrace(); // doStats needs to see the next record
}
// if(Simulator.CurrentRound > 650000 && m_ID ==15)
// Console.WriteLine("core:{1} after advancetrace in DOSTEP: cyc {0}, ID = {1}, trace_valid = {2}, retiring {3} instructions, isfull = {4}", Simulator.CurrentRound, m_ID, m_trace_valid, retired, m_ins.isFull());
// Console.WriteLine("core:{1} before stat: cyc {0}", Simulator.CurrentRound, m_ID);
doStats(retired);
if (m_ins.isFull())
{
return(true);
}
bool done = false;
int nIns = Config.proc.instructionsPerCycle;
if (m_is_GPU)
{
nIns = Config.proc.GPUinstructionsPerCycle;
}
else if (Config.CPU == false)
{
done = true;
}
int nMem = 1;
// if(Simulator.CurrentRound > 650000 && m_ID ==15)
// Console.WriteLine("core:{1} before loop: cyc {0}, ID = {1} done = {2}, numIns = {3}, isFull = {4}", Simulator.CurrentRound, m_ID, done, nIns, m_ins.isFull());
while (!done && nIns > 0 && !m_ins.isFull())
{
// if(Simulator.CurrentRound > 700000 && m_ID ==15)
// Console.WriteLine("cycle:{0} in loop before advance trace, trace valid = {1} ", Simulator.CurrentRound, m_trace_valid);
if (!m_trace_valid)
{
// if(Simulator.CurrentRound > 700000 && m_ID ==15)
// Console.WriteLine("cycle:{0} in loop after advance trace, trace valid = {1} ", Simulator.CurrentRound, m_trace_valid);
m_trace_valid = advanceTrace();
}
if (!m_trace_valid)
{
return(false);
}
if (m_trace.type == Trace.Type.Pause) // when execution-driven, source has nothing to give
{
m_trace_valid = false;
return(true);
}
if (m_trace.type == Trace.Type.Sync)
{
// `from' field: translate referrent from thd ID to physical CPU id
syncID = Simulator.network.workload.mapThd(m_group, m_trace.from);
}
else
{
syncID = m_trace.from;
}
switch (m_trace.type)
{
case Trace.Type.Rd:
case Trace.Type.Wr:
if (nMem == 0 || !canIssueMSHR(m_trace.address))
{
done = true;
break;
}
nMem--;
nIns--;
if (m_is_GPU)
{
deadLineReqCnt++;
}
ulong addr = m_trace.address;
bool isWrite = m_trace.type == Trace.Type.Wr;
bool inWindow = m_ins.contains(addr, isWrite);
int windowID = m_ins.next;
Request req = inWindow ? null : new Request(m_ID, addr, isWrite);
/* HWA CODE */
if (m_is_HWA)
{
deadLineReqFetchCnt++;
// if( !inWindow ) req.setDeadLine( deadLine, deadLineCnt, deadLineReq, deadLineReqCnt );
}
/* HWA CODE END */
m_ins.fetch(req, addr, isWrite, inWindow);
// if(Simulator.CurrentRound > 700000 && m_ID ==15)
// Console.WriteLine("core:{1} in loop - mem: cyc {0}, inWindow = {1}", Simulator.CurrentRound, m_ID, inWindow);
if (!inWindow)
{
if (!m_is_GPU)
{
issueReq(req, windowID);
}
else
{
req.from_GPU = true;
req.memsize = ((TraceFile_AMD_GPU)m_trace).memsize;
req.client = ((TraceFile_AMD_GPU)m_trace).client;
issueReq(req, windowID);
}
}
m_trace_valid = false;
break;
case Trace.Type.NonMem:
if (m_trace.address > 0)
{
// Console.WriteLine("core:{1} in loop - nonmem before fetch: cyc {0}", Simulator.CurrentRound, m_ID);
m_ins.fetch(null, InstructionWindow.NULL_ADDRESS, false, true);
m_trace.address--;
nIns--;
}
else
{
m_trace_valid = false;
}
break;
case Trace.Type.Label:
if (m_sync.Label(m_ID, syncID, m_trace.address))
{
m_trace_valid = false; // allowed to continue
}
else
{ // shouldn't ever block...
if (m_stats_active)
{
Simulator.stats.cpu_sync_memdep[m_ID].Add();
}
done = true; // blocking: done with this cycle
}
break;
case Trace.Type.Sync:
if (m_sync.Sync(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{
if (m_stats_active)
{
Simulator.stats.cpu_sync_memdep[m_ID].Add();
}
done = true;
}
break;
case Trace.Type.Lock:
//Console.WriteLine("Lock" + ' ' + m_ID.ToString() + ' ' + syncID.ToString() + ' ' + m_trace.address.ToString());
if (m_sync.Lock(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{
if (m_stats_active)
{
Simulator.stats.cpu_sync_lock[m_ID].Add();
}
done = true;
}
break;
case Trace.Type.Unlock:
//Console.WriteLine("Unlock" + ' ' + m_ID.ToString() + ' ' + syncID.ToString() + ' ' + m_trace.address.ToString());
if (m_sync.Unlock(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{ // shouldn't ever block...
if (m_stats_active)
{
Simulator.stats.cpu_sync_lock[m_ID].Add();
}
done = true;
}
break;
case Trace.Type.Barrier:
//Console.WriteLine("Barrier" + ' ' + m_ID.ToString() + ' ' + syncID.ToString() + ' ' + m_trace.address.ToString());
if (m_sync.Barrier(m_ID, syncID, m_trace.address))
{
m_trace_valid = false;
}
else
{
if (m_stats_active)
{
Simulator.stats.cpu_sync_barrier[m_ID].Add();
}
done = true;
}
break;
}
// Console.WriteLine("core:{1} in loop - at the end: cyc {0}", Simulator.CurrentRound, m_ID);
}
// Console.WriteLine("core:{1} after loop: cyc {0}", Simulator.CurrentRound, m_ID);
return(true);
}