private LibraryElement GetBEL(BELInfo info) { LibraryElement element = new LibraryElement { SliceNumber = SliceNumber, Name = info.belName, PrimitiveName = BELType, BEL = info.belName, LoadCommand = ToString(), Containter = new XDLModule(), VHDLGenericMap = info.type.VHDLGenericMap, VivadoConnectionPrimitive = true }; // Outputs foreach (string output in info.type.outputNames) { element.Containter.Add(MakeXDLPort(output, FPGATypes.PortDirection.Out)); } // Inputs foreach (string input in info.type.inputNames) { element.Containter.Add(MakeXDLPort(input, FPGATypes.PortDirection.In, info.type.inputsConstantValue)); } // Get first encountered clb ?! Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)); Tile interconnect = FPGATypes.GetInterconnectTile(clb); if (info.traverseBackwards) { TraverseBackwards(element, clb, interconnect, info); } foreach (string stopOverPortName in StopOverPorts) { element.AddPortToBlock(interconnect, new Port(stopOverPortName)); } return(element); }
private LibraryElement GetOtherElement(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort) { BELInfo info = new BELInfo { belName = belName, makeInputsConstant = makeInputsConstant, inputPortPrefix = inputPortPrefix, outputPort = outputPort }; BELType?type = VivadoBELManager.Instance.GetBELType(BELType); if (type != null) { info.traverseBackwards = false; info.type = (BELType)type; // if (type == LUT6) type.Value.inputsConstantValue = makeInputsConstant return(GetBEL(info)); } throw new ArgumentException("Unsupported BEL Type: " + BELType); }
private void TraverseBackwards(LibraryElement element, Tile clb, Tile interconnect, BELInfo info) { List <string> lutPortNames = new List <string>(); // see LUTRouting tab for (int i = 1; i <= info.type.inputNames.Count; i++) { lutPortNames.Add(info.inputPortPrefix + i); } foreach (string s in lutPortNames) { // travers backwards into INT foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => a.Item2.Name.EndsWith(s))) { element.AddPortToBlock(clb, t.Item1); element.AddPortToBlock(clb, t.Item2); if (interconnect.WireList == null) { OutputManager.WriteWarning("No wire list found on " + interconnect.Location); } else { foreach (Wire w in interconnect.WireList.Where(w => w.PipOnOtherTile.Equals(t.Item1.Name))) { element.AddPortToBlock(interconnect, new FPGA.Port(w.LocalPip)); } } } } // we always need to exclude the port from the LUT output from blocking // assuming name foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => a.Item1.Name.EndsWith(info.outputPort))) { // no realy neccessary element.AddPortToBlock(clb, t.Item1); element.AddPortToBlock(clb, t.Item2); foreach (Wire w in clb.WireList.Where(w => w.LocalPip.Equals(t.Item2.Name))) { element.AddPortToBlock(interconnect, new Port(w.PipOnOtherTile)); } } }