private void ProcessNextNetLine(char[] buffer, int size, XDLNet net)
{
string[] atoms = null;
try
{
atoms = m_splitNetLineWhiteSpaceOnly.Split(new string(buffer, 0, size));
}
catch
{
Console.WriteLine(size);
Console.WriteLine(buffer);
Console.WriteLine(net);
}
for (int i = 0; i < atoms.Length; i++)
{
if (atoms[i].Equals("pip"))
{
string location = atoms[i + 1];
string from = atoms[i + 2];
string op = atoms[i + 3];
string to = atoms[i + 4].Replace(",", "");
XDLPip pip = new XDLPip(location, from, op, to);
net.Add(pip);
return;
}
else if (atoms[i].Equals("inpin"))
{
NetInpin inpin = new NetInpin();
inpin.InstanceName = atoms[i + 1];
inpin.SlicePort = atoms[i + 2];
net.Add(Trim(inpin));
return;
}
else if (atoms[i].Equals("outpin"))
{
NetOutpin outpin = new NetOutpin();
outpin.InstanceName = atoms[i + 1];
outpin.SlicePort = atoms[i + 2];
net.Add(Trim(outpin));
return;
}
else if (atoms[i].Equals("cfg"))
{
//net.Config = "cfg ";
for (int j = 0; j < size; j++)
{
net.Config += buffer[j];
}
return;
}
}
}
public override NetlistContainer GetSelectedDesignElements()
{
// resulting design
XDLContainer result = new XDLContainer();
result.Name = Name;
result.AddDesignConfig(GetDesignConfig());
// copy modules
foreach (XDLModule mod in Modules)
{
result.Add(mod);
}
// filter ports
foreach (XDLPort p in Ports)
{
XDLInstance inst = (XDLInstance)GetInstanceByName(p.InstanceName);
if (TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
result.Add(p);
}
}
// filter instances
foreach (XDLInstance inst in Instances)
{
if (TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
result.Add(inst);
}
}
// filter nets
foreach (XDLNet inNet in Nets)
{
XDLNet outNet = new XDLNet();
outNet.Name = inNet.Name;
outNet.Header = inNet.Header;
outNet.HeaderExtension = inNet.HeaderExtension;
outNet.Config = inNet.Config;
bool arcAdded = false;
//outNet.AddCode(inNet.Header);
// add/remove pins
foreach (NetPin pin in inNet.NetPins)
{
TileKey where = GetInstanceByName(pin.InstanceName).TileKey;
if (TileSelectionManager.Instance.IsSelected(where))
{
outNet.Add(pin);
arcAdded = true;
}
}
// add/remoce pips (arcs)
foreach (XDLPip pip in inNet.Pips)
{
bool addPip = true;
if (HasMappedInstances(pip.Location))
{
// exclude via instance
foreach (XDLInstance inst in GetInstancesByLocation(pip.Location))
{
if (!TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
addPip = false;
break;
}
}
}
else
{
// exclude via TileKey (eg for tile without instances INT_X8Y36)
Tile where = FPGA.FPGA.Instance.GetTile(pip.Location);
if (!TileSelectionManager.Instance.IsSelected(where.TileKey))
{
addPip = false;
}
}
if (addPip)
{
// we keep this net
arcAdded = true;
outNet.Add(pip);
}
}
// only add non empty nets
if (arcAdded)
{
result.Add(outNet);
}
}
return(result);
}