public override void ParseDesign(NetlistContainer nlc, Command caller)
{
XDLContainer xdlContainer = (XDLContainer)nlc;
bool readNet = false;
bool readDesign = false;
bool readModule = false;
bool readInstance = false;
XDLNet net = null;
XDLInstance inst = null;
XDLModule module = null;
char[] buffer = new char[1];
bool pendingQuote = false;
StringBuilder designConfig = new StringBuilder();
StringBuilder lineBuffer = new StringBuilder();
Regex anchorMatch = new Regex("^\".*\"$", RegexOptions.Compiled);
Regex whiteSpaceMatch = new Regex(@"\s+", RegexOptions.Compiled);
FileInfo fi = new FileInfo(m_fileName);
int length = (int)fi.Length;
char c = ' ';
char[] modReferenceBuffer = new char[2048];
int modReferenceBufferIndex = 0;
char[] keyWordBuffer = new char[2048];
int keyWordBufferIndex = 0;
char[] locationBuffer = new char[2048];
char[] fromBuffer = new char[32];
char[] toBuffer = new char[32];
StreamReader sr = new StreamReader(m_fileName);
int charIndex = 0;
while (charIndex < length)
{
// get next char
c = (char)sr.Read(); charIndex++;
// measure progress
if (caller != null)
{
caller.ProgressInfo.Progress = (int)((double)charIndex / (double)length * 100);
}
// skip comments
while (c == '#' && !readNet && !readInstance && !readDesign && !readModule)
{
while (true)
{
c = (char)sr.Read();
charIndex++;
if (c == '\n')
{
break;
}
}
c = (char)sr.Read(); charIndex++;
}
if (readNet)
{
ReadNet(net, c, sr, ref charIndex, length, caller);
readNet = false;
if (readModule)
{
module.Add(net);
}
else
{
xdlContainer.Add(net);
}
lineBuffer.Clear();
}
else if (readInstance)
{
ReadInstance(inst, c, sr, ref charIndex);
readInstance = false;
if (readModule)
{
module.Add(inst);
}
else
{
xdlContainer.Add(inst);
}
lineBuffer.Clear();
}
else
{
keyWordBufferIndex = 0;
switch (c)
{
case 'n':
// read everything until first comma outside quotes
// net "Inst_PE/Mmult_OPA[31]_OPB[31]_MuLt_18_OUT_OPA,OPB<10>_x_OPA,OPB<62>_mand1_FRB"
pendingQuote = false;
keyWordBuffer[keyWordBufferIndex++] = c;
while (true)
{
//c = (char)byteBuffer[charIndex++];
c = (char)sr.Read(); charIndex++;
keyWordBuffer[keyWordBufferIndex++] = c;
if (c == '"')
{
pendingQuote = !pendingQuote;
}
if (c == ',' && !pendingQuote)
{
break;
}
}
readNet = true;
break;
case 'c':
// read everything until first ; outside quotes
// may appear anywhere and will be ignore (Jo)
//cfg "
//# _DESIGN_PROP:P3_PLACE_OPTIONS:EFFORT_LEVEL:high
//# _DESIGN_PROP::P3_PLACED:
//# _DESIGN_PROP::P3_PLACE_OPTIONS:
//# _DESIGN_PROP::PK_NGMTIMESTAMP:1397048215";
pendingQuote = false;
keyWordBuffer[keyWordBufferIndex++] = c;
while (true)
{
c = (char)sr.Read(); charIndex++;
keyWordBuffer[keyWordBufferIndex++] = c;
if (c == '"')
{
pendingQuote = !pendingQuote;
}
if (c == ';' && !pendingQuote)
{
break;
}
}
break;
case 'i':
// read two commas outside qoutes
// inst "Inst_PE/Mmult_OPA[31]_OPB[31]_MuLt_18_OUT_OPA,OPB<21>_x_OPA,OPB<62>_mand1_FRB" "SLICEL",placed CLBLM_X18Y191 SLICE_X27Y191 ,
pendingQuote = false;
int commas = 0;
keyWordBuffer[keyWordBufferIndex++] = c;
while (commas != 2)
{
//c = (char)byteBuffer[charIndex++];
c = (char)sr.Read();
charIndex++;
keyWordBuffer[keyWordBufferIndex++] = c;
if (c == '"')
{
pendingQuote = !pendingQuote;
}
if (c == ',' && !pendingQuote)
{
commas++;
}
}
readInstance = true;
break;
case 'd':
designConfig.Append(c);
while (true)
{
c = (char)sr.Read(); charIndex++;
designConfig.Append(c);
if (c == ';')
{
break;
}
}
string[] atoms = whiteSpaceMatch.Split(designConfig.ToString());
// do not modify name here
if (xdlContainer.DesignName == null)
{
xdlContainer.DesignName = Regex.Replace(atoms[1], "\"", "");
xdlContainer.Family = (atoms.Length > 3 ? Regex.Replace(atoms[2], "\"", "") : "unknown");
xdlContainer.AddDesignConfig(designConfig.ToString());
}
else
{
caller.OutputManager.WriteWarning("Ignoring the device config as there is already a device name " + xdlContainer.DesignName + " present");
}
if (!FPGA.FPGA.Instance.DeviceName.ToString().Equals(xdlContainer.Family) && !xdlContainer.Family.Equals("unknown"))
{
// TODO wenn das obige if GARANTIERT "tut", dann kann man auch eine ArgumentException werden
caller.OutputManager.WriteWarning("The currenlty loaded device is " + FPGA.FPGA.Instance.DeviceName + ". However, the device specified in the currently parsed in netlist is " + xdlContainer.Family);
}
break;
case 'm':
module = new XDLModule();
readModule = true;
string moduleHeader = "";
moduleHeader += c;
while (true)
{
if (charIndex >= length)
{
throw new ArgumentException("Unexpected end of file while reading module. Missing endmodule statement?");
}
c = (char)sr.Read(); charIndex++;
moduleHeader += c;
if (c == ';')
{
break;
}
}
moduleHeader = Regex.Replace(moduleHeader, @"^\s*", "");
string[] moduleAtoms = whiteSpaceMatch.Split(moduleHeader);
// extract module
module.Name = Regex.Replace(moduleAtoms[1], "\"", "");
module.Name = Regex.Replace(module.Name, ",", "");
// names is used as a key
xdlContainer.Add(module);
// extract explicit anchor
string anchor = moduleAtoms[2];
module.ExplicitAnchorFound = anchorMatch.IsMatch(anchor);
if (module.ExplicitAnchorFound)
{
module.Anchor = Regex.Replace(anchor, "\"", "");
}
break;
case 'p':
//port "H0" "SliceInstance" "A6";
ReadPort(module, c, sr, ref charIndex);
break;
case 'e': // endmodule
while (true)
{
c = (char)sr.Read(); charIndex++;
if (c == ';')
{
break;
}
}
readModule = false;
break;
}
string s = new string(keyWordBuffer, 0, keyWordBufferIndex);
if (readNet)
{
net = new XDLNet();
net.Header = s;
List <string> atoms = SplitLine(s);
for (int i = 0; i < atoms.Count; i++)
{
if (atoms[i].Equals("net"))
{
net.Name = atoms[i + 1];
net.Name = net.Name.Replace("\"", "");
if (atoms.Count > i + 2)
{
net.HeaderExtension = atoms[i + 2];
}
break;
}
}
lineBuffer.Clear();
}
else if (readInstance)
{
inst = new XDLInstance();
List <string> atoms = SplitLine(s);
inst.AddCode(s);
for (int i = 0; i < atoms.Count; i++)
{
if (atoms[i].Equals("inst"))
{
//inst.Name = Regex.Replace(atoms[i + 1], "\"", "");
inst.Name = atoms[i + 1];
inst.Name = inst.Name.Replace("\"", "");
//inst.SliceType = Regex.Replace(atoms[i + 2], "\"", "");
inst.SliceType = atoms[i + 2];
inst.SliceType = inst.SliceType.Replace("\"", "");
}
else if (atoms[i].Equals("placed"))
{
string[] locationAtoms = atoms[i + 1].Split('X', 'Y');
inst.LocationX = int.Parse(locationAtoms[locationAtoms.Length - 2]);
inst.LocationY = int.Parse(locationAtoms[locationAtoms.Length - 1]);
inst.Location = atoms[i + 1];
inst.SliceName = atoms[i + 2];
break;
}
}
c = (char)sr.Read(); charIndex++;
if (c != 'm') // should be \r
{
inst.AddCode(c);
}
else
{
modReferenceBufferIndex = 0;
// consume module reference (will not become part of the module)
modReferenceBuffer[modReferenceBufferIndex++] = c;
while (true)
{
c = (char)sr.Read(); charIndex++;
modReferenceBuffer[modReferenceBufferIndex++] = c;
if (c == ',')
{
break;
}
}
inst.ModuleReference = new string(modReferenceBuffer, 0, modReferenceBufferIndex);
}
}
}
}
sr.Close();
}
public void WriteXDLCodeToFile(StreamWriter sw)
{
if (m_includeDesignStatement)
{
// design "__XILINX_NMC_MACRO" 2v500fg256-5;
sw.WriteLine("design \"" + m_designName + "\" " + FPGA.FPGA.Instance.DeviceName + ";");
if (m_includeModuleHeader)
{
// set the anchor to the op left slice of all macros
string anchor;
bool anchorFound = XDLContainer.GetAnchor(m_netlistContainer, out anchor);
// module "BtnBar" "SLICE_X60Y148" , cfg "_SYSTEM_MACRO::FALSE" ;
sw.WriteLine("module \"" + GetModuleName() + "\"" + (anchorFound ? " \"" + anchor + "\"" : "") + ", cfg \"_SYSTEM_MACRO::FALSE\";");
sw.WriteLine("");
}
}
else if (m_netlistContainer.Count > 0)
{
// print the first header
string designConfig = m_netlistContainer[0].GetDesignConfig();
if (designConfig.Length > 0)
{
sw.WriteLine(designConfig);
}
else
{
// generate default header
sw.WriteLine("design \"" + m_designName + "\" " + FPGA.FPGA.Instance.DeviceName + " v3.2 ,");
sw.WriteLine("cfg \"");
sw.WriteLine("\t" + "_DESIGN_PROP:P3_PLACE_OPTIONS:EFFORT_LEVEL:high");
sw.WriteLine("\t" + "_DESIGN_PROP::P3_PLACED:");
sw.WriteLine("\t" + "_DESIGN_PROP::P3_PLACE_OPTIONS:");
sw.WriteLine("\t" + "_DESIGN_PROP::PK_NGMTIMESTAMP:1397048215\";");
}
}
foreach (XDLContainer n in m_netlistContainer)
{
foreach (XDLModule mod in n.Modules)
{
sw.WriteLine(mod.ToString());
}
}
if (m_exportPortDeclarations)
{
foreach (XDLContainer n in m_netlistContainer)
{
foreach (XDLMacroPort port in n.MacroPorts)
{
sw.WriteLine(GetCode(port));
}
sw.WriteLine(n.GetNetPortsBlocks());
}
}
sw.WriteLine("");
int instCount = 0;
foreach (XDLContainer n in m_netlistContainer)
{
foreach (Slice s in n.GetAllSlicesTemplates().OrderBy(s => s.SliceName))
{
sw.WriteLine(GetCode(s));
instCount++;
}
foreach (XDLInstance inst in n.Instances.OrderBy(i => i.InstanceIndex))
{
sw.WriteLine(inst.ToString());
instCount++;
}
}
sw.WriteLine("");
/*
* foreach (NetlistContainer n in this.m_netlistContainer)
* {
* foreach (Tile t in n.GetAllRAMTemplates())
* {
* sw.WriteLine(this.GetCode(t));
* }
* }*/
int netCount = 0;
if (m_exportDummyNets)
{
sw.WriteLine("");
foreach (XDLContainer n in m_netlistContainer)
{
foreach (XDLMacroPort p in n.MacroPorts)
{
sw.WriteLine(GetDummyNetCode(p));
netCount++;
}
// e.g. dummy blocker nets form template
n.WriteNetCodeBlocks(sw);
}
}
sw.WriteLine("");
foreach (XDLContainer nlc in m_netlistContainer)
{
foreach (XDLNet n in nlc.Nets)
{
// blocker nets become very huge ...
n.WriteToFile(sw);
netCount++;
}
}
sw.WriteLine("");
if (m_includeModuleFooter)
{
sw.WriteLine("endmodule \"" + GetModuleName() + "\";");
}
sw.WriteLine("# =======================================================");
sw.WriteLine("# SUMMARY");
sw.WriteLine("# Number of Module Defs: 0");
sw.WriteLine("# Number of Module Insts: 0");
sw.WriteLine("# Number of Primitive Insts: " + instCount);
sw.WriteLine("# Number of Nets: " + netCount);
sw.WriteLine("# =======================================================");
}
public override NetlistContainer GetSelectedDesignElements()
{
// resulting design
XDLContainer result = new XDLContainer();
result.Name = Name;
result.AddDesignConfig(GetDesignConfig());
// copy modules
foreach (XDLModule mod in Modules)
{
result.Add(mod);
}
// filter ports
foreach (XDLPort p in Ports)
{
XDLInstance inst = (XDLInstance)GetInstanceByName(p.InstanceName);
if (TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
result.Add(p);
}
}
// filter instances
foreach (XDLInstance inst in Instances)
{
if (TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
result.Add(inst);
}
}
// filter nets
foreach (XDLNet inNet in Nets)
{
XDLNet outNet = new XDLNet();
outNet.Name = inNet.Name;
outNet.Header = inNet.Header;
outNet.HeaderExtension = inNet.HeaderExtension;
outNet.Config = inNet.Config;
bool arcAdded = false;
//outNet.AddCode(inNet.Header);
// add/remove pins
foreach (NetPin pin in inNet.NetPins)
{
TileKey where = GetInstanceByName(pin.InstanceName).TileKey;
if (TileSelectionManager.Instance.IsSelected(where))
{
outNet.Add(pin);
arcAdded = true;
}
}
// add/remoce pips (arcs)
foreach (XDLPip pip in inNet.Pips)
{
bool addPip = true;
if (HasMappedInstances(pip.Location))
{
// exclude via instance
foreach (XDLInstance inst in GetInstancesByLocation(pip.Location))
{
if (!TileSelectionManager.Instance.IsSelected(inst.TileKey))
{
addPip = false;
break;
}
}
}
else
{
// exclude via TileKey (eg for tile without instances INT_X8Y36)
Tile where = FPGA.FPGA.Instance.GetTile(pip.Location);
if (!TileSelectionManager.Instance.IsSelected(where.TileKey))
{
addPip = false;
}
}
if (addPip)
{
// we keep this net
arcAdded = true;
outNet.Add(pip);
}
}
// only add non empty nets
if (arcAdded)
{
result.Add(outNet);
}
}
return(result);
}