static void Main(string[] args)
{
testbench_XilinxDivider tb = new testbench_XilinxDivider();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(100 * testbench_XilinxDivider.ClockPeriod);
//DesignContext.Instance.Simulate(10 * (testbench_XilinxDivider_.DataWidth + 3) * testbench_XilinxDivider_.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "XilinxDivider");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
static void Main(string[] args)
{
testbench_XilinxDivider tb = new testbench_XilinxDivider();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(100 * testbench_XilinxDivider.ClockPeriod);
//DesignContext.Instance.Simulate(10 * (testbench_XilinxDivider_.DataWidth + 3) * testbench_XilinxDivider_.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_output", "XilinxDivider");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
