public static void Ushl_V(ILEmitterCtx context) { OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; for (int index = 0; index < elems; index++) { EmitVectorExtractZx(context, op.Rn, index, op.Size); EmitVectorExtractZx(context, op.Rm, index, op.Size); context.Emit(OpCodes.Ldc_I4_0); context.EmitLdc_I4(op.Size); SoftFallback.EmitCall(context, nameof(SoftFallback.UnsignedShlReg)); EmitVectorInsert(context, op.Rd, index, op.Size); } if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } }
// TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned). public static void EmitSatQ( ILEmitterCtx context, int sizeDst, bool signedSrc, bool signedDst) { if (sizeDst > 2) { throw new ArgumentOutOfRangeException(nameof(sizeDst)); } context.EmitLdc_I4(sizeDst); context.EmitLdarg(TranslatedSub.StateArgIdx); if (signedSrc) { SoftFallback.EmitCall(context, signedDst ? nameof(SoftFallback.SignedSrcSignedDstSatQ) : nameof(SoftFallback.SignedSrcUnsignedDstSatQ)); } else { SoftFallback.EmitCall(context, signedDst ? nameof(SoftFallback.UnsignedSrcSignedDstSatQ) : nameof(SoftFallback.UnsignedSrcUnsignedDstSatQ)); } }
// dst64 = (Int(src64, signed) + roundConst) >> shift; private static void EmitShrImm64(ILEmitterCtx context, bool signed, long roundConst, int shift) { context.EmitLdc_I8(roundConst); context.EmitLdc_I4(shift); SoftFallback.EmitCall(context, signed ? nameof(SoftFallback.SignedShrImm64) : nameof(SoftFallback.UnsignedShrImm64)); }
public static void Sha1h_V(ILEmitterCtx context) { OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; EmitVectorExtractZx(context, op.Rn, 0, 2); SoftFallback.EmitCall(context, nameof(SoftFallback.FixedRotate)); EmitScalarSet(context, op.Rd, 2); }
public static void Rev64(ILEmitterCtx context) { OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp; context.EmitLdintzr(op.Rn); SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBytes64)); context.EmitStintzr(op.Rd); }
public static void Aesmc_V(ILEmitterCtx context) { OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; context.EmitLdvec(op.Rn); SoftFallback.EmitCall(context, nameof(SoftFallback.MixColumns)); context.EmitStvec(op.Rd); }
public static void Umulh(ILEmitterCtx context) { OpCodeMul64 op = (OpCodeMul64)context.CurrOp; context.EmitLdintzr(op.Rn); context.EmitLdintzr(op.Rm); SoftFallback.EmitCall(context, nameof(SoftFallback.UMulHi128)); context.EmitStintzr(op.Rd); }
// TSrc (64bit) == TDst (64bit); signed. public static void EmitUnarySignedSatQAbsOrNeg(ILEmitterCtx context) { if (((OpCodeSimd64)context.CurrOp).Size < 3) { throw new InvalidOperationException(); } context.EmitLdarg(TranslatedSub.StateArgIdx); SoftFallback.EmitCall(context, nameof(SoftFallback.UnarySignedSatQAbsOrNeg)); }
public static void Sha1su1_V(ILEmitterCtx context) { OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rn); SoftFallback.EmitCall(context, nameof(SoftFallback.Sha1SchedulePart2)); context.EmitStvec(op.Rd); }
public static void Cls(ILEmitterCtx context) { OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp; context.EmitLdintzr(op.Rn); context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64); SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingSigns)); context.EmitStintzr(op.Rd); }
public static void Sha256h_V(ILEmitterCtx context) { OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp; context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rm); SoftFallback.EmitCall(context, nameof(SoftFallback.HashLower)); context.EmitStvec(op.Rd); }
public static void Sha1p_V(ILEmitterCtx context) { OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp; context.EmitLdvec(op.Rd); EmitVectorExtractZx(context, op.Rn, 0, 2); context.EmitLdvec(op.Rm); SoftFallback.EmitCall(context, nameof(SoftFallback.HashParity)); context.EmitStvec(op.Rd); }
// TSrcs (64bit) == TDst (64bit); signed, unsigned. public static void EmitBinarySatQAccumulate(ILEmitterCtx context, bool signed) { if (((OpCodeSimd64)context.CurrOp).Size < 3) { throw new InvalidOperationException(); } context.EmitLdarg(TranslatedSub.StateArgIdx); SoftFallback.EmitCall(context, signed ? nameof(SoftFallback.BinarySignedSatQAcc) : nameof(SoftFallback.BinaryUnsignedSatQAcc)); }
private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64) { OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp; context.EmitLdintzr(op.Rn); if (op.RegisterSize == RegisterSize.Int32) { SoftFallback.EmitCall(context, name32); } else { SoftFallback.EmitCall(context, name64); } context.EmitStintzr(op.Rd); }
public static void Clz(ILEmitterCtx context) { OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp; context.EmitLdintzr(op.Rn); if (Lzcnt.IsSupported) { Type tValue = op.RegisterSize == RegisterSize.Int32 ? typeof(uint) : typeof(ulong); context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { tValue })); } else { context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64); SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingZeros)); } context.EmitStintzr(op.Rd); }
private static void EmitCrc32(ILEmitterCtx context, string name) { OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp; context.EmitLdintzr(op.Rn); if (op.RegisterSize != RegisterSize.Int32) { context.Emit(OpCodes.Conv_U4); } context.EmitLdintzr(op.Rm); SoftFallback.EmitCall(context, name); if (op.RegisterSize != RegisterSize.Int32) { context.Emit(OpCodes.Conv_U8); } context.EmitStintzr(op.Rd); }
public static void Rbit_V(ILEmitterCtx context) { OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8; for (int index = 0; index < elems; index++) { EmitVectorExtractZx(context, op.Rn, index, 0); context.Emit(OpCodes.Conv_U4); SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBits8)); context.Emit(OpCodes.Conv_U8); EmitVectorInsert(context, op.Rd, index, 0); } if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } }