//NETLIB_CONSTRUCTOR(NE555)
public nld_NE555(object owner, string name)
: base(owner, name)
{
m_R1 = new analog.nld_R_base(this, "R1");
m_R2 = new analog.nld_R_base(this, "R2");
m_R3 = new analog.nld_R_base(this, "R3");
m_ROUT = new analog.nld_R_base(this, "ROUT");
m_RDIS = new analog.nld_R_base(this, "RDIS");
m_RESET = new logic_input_t(this, "RESET", inputs); // Pin 4
m_THRES = new analog_input_t(this, "THRESH", inputs); // Pin 6
m_TRIG = new analog_input_t(this, "TRIG", inputs); // Pin 2
m_OUT = new analog_output_t(this, "_OUT"); // to Pin 3 via ROUT
m_last_out = new state_var <bool>(this, "m_last_out", false);
m_ff = new state_var <bool>(this, "m_ff", false);
m_last_reset = new state_var <bool>(this, "m_last_reset", false);
m_overshoot = new state_var <nl_fptype>(this, "m_overshoot", 0.0);
m_undershoot = new state_var <nl_fptype>(this, "m_undershoot", 0.0);
m_ovlimit = 0.0;
register_subalias("GND", "R3.2"); // Pin 1
register_subalias("CONT", "R1.2"); // Pin 5
register_subalias("DISCH", "RDIS.1"); // Pin 7
register_subalias("VCC", "R1.1"); // Pin 8
register_subalias("OUT", "ROUT.1"); // Pin 3
connect("R1.2", "R2.1");
connect("R2.2", "R3.1");
connect("RDIS.2", "R3.2");
connect("_OUT", "ROUT.2");
}
void push_to_queue(netlist_time delay)
{
if (!!is_queued())
{
exec().qremove(this);
}
m_next_scheduled_time.op = exec().time() + delay;
#if (AVOID_NOOP_QUEUE_PUSHES)
m_in_queue = (m_list_active.empty() ? queue_status::DELAYED_DUE_TO_INACTIVE
: (m_new_Q != m_cur_Q ? queue_status::QUEUED : queue_status::DELIVERED));
if (m_in_queue == queue_status::QUEUED)
{
exec().qpush(m_next_scheduled_time, this);
}
else
{
update_inputs();
}
#else
m_in_queue.op = m_list_active.empty() ? queue_status.DELAYED_DUE_TO_INACTIVE : queue_status.QUEUED;
if (m_in_queue.op == queue_status.QUEUED)
{
exec().qpush(new plib.pqentry_t <netlist_time, net_t>(m_next_scheduled_time.op, this));
}
else
{
update_inputs();
}
#endif
}
generic_capacitor_variable(core_device_t dev, string name)
{
m_h = new state_var <nl_fptype>(dev, name + ".m_h", nlconst.zero());
m_c = new state_var <nl_fptype>(dev, name + ".m_c", nlconst.zero());
m_v = new state_var <nl_fptype>(dev, name + ".m_v", nlconst.zero());
m_gmin = nlconst.zero();
}
//NETLIB_CONSTRUCTOR_EX(analog_callback, nl_fptype threshold, FUNC &&func)
public nld_analog_callback(object owner, string name, nl_fptype threshold, FUNC func)
: base(owner, name)
{
m_in = new analog_input_t(this, "IN", in_);
m_threshold = threshold;
m_last = new state_var <nl_fptype>(this, "m_last", 0);
m_func = func;
}
//NETLIB_CONSTRUCTOR_MODEL(CD4066_GATE, "CD4XXX")
public nld_CD4066_GATE(object owner, string name)
: base(owner, name, "CD4XXX")
{
m_R = new analog.nld_R_base(this, "R");
m_control = new analog_input_t(this, "CTL", control);
m_base_r = new param_fp_t(this, "BASER", nlconst.magic(270.0));
m_last = new state_var <bool>(this, "m_last", false);
m_supply = new nld_power_pins(this);
}
//NETLIB_CONSTRUCTOR(74153)
public nld_74153(object owner, string name)
: base(owner, name)
{
m_C = new object_array_t_logic_input_t <u64_const_4>(this, new logic_input_t(this, "C0", sub), new logic_input_t(this, "C1", sub), new logic_input_t(this, "C2", sub), new logic_input_t(this, "C3", sub));
m_G = new logic_input_t(this, "G", sub);
m_Y = new logic_output_t(this, "AY"); //FIXME: Change netlists
m_chan = new state_var <unsigned>(this, "m_chan", 0);
m_A = new logic_input_t(this, "A", other);
m_B = new logic_input_t(this, "B", other);
m_power_pins = new nld_power_pins(this);
}
protected net_t(netlist_state_t nl, string aname, core_terminal_t railterminal = null)
: base(nl.exec(), aname)
{
m_new_Q = new state_var <netlist_sig_t>(this, "m_new_Q", (netlist_sig_t)0);
m_cur_Q = new state_var <netlist_sig_t>(this, "m_cur_Q", (netlist_sig_t)0);
m_in_queue = new state_var <queue_status>(this, "m_in_queue", queue_status.DELIVERED);
m_next_scheduled_time = new state_var <netlist_time_ext>(this, "m_time", netlist_time_ext.zero());
m_railterminal = railterminal;
object_t_props.add(this, ""); //props::add(this, props::value_type());
}
//NETLIB_CONSTRUCTOR(7474)
public nld_7474(object owner, string name)
: base(owner, name)
{
m_D = new logic_input_t(this, "D", inputs);
m_CLRQ = new logic_input_t(this, "CLRQ", inputs);
m_PREQ = new logic_input_t(this, "PREQ", inputs);
m_CLK = new logic_input_t(this, "CLK", clk);
m_Q = new logic_output_t(this, "Q");
m_QQ = new logic_output_t(this, "QQ");
m_nextD = new state_var <netlist_sig_t>(this, "m_nextD", 0);
m_power_pins = new nld_power_pins(this);
}
//NETLIB_CONSTRUCTOR(7493)
public nld_7493(object owner, string name)
: base(owner, name)
{
m_CLKA = new logic_input_t(this, "CLKA", updA);
m_CLKB = new logic_input_t(this, "CLKB", updB);
m_QA = new logic_output_t(this, "QA");
m_QB = new object_array_t_logic_output_t <u64_const_3>(this, new logic_output_t(this, "QB"), new logic_output_t(this, "QC"), new logic_output_t(this, "QD"));
m_a = new state_var <unsigned>(this, "m_a", 0);
m_bcd = new state_var <unsigned>(this, "m_b", 0);
m_R1 = new logic_input_t(this, "R1", inputs);
m_R2 = new logic_input_t(this, "R2", inputs);
m_power_pins = new nld_power_pins(this);
}
//NETLIB_CONSTRUCTOR(sys_dsw1)
//detail.family_setter_t m_famsetter;
//template <class CLASS>
public nld_sys_dsw1(object owner, string name)
: base(owner, name)
{
m_RON = new param_fp_t(this, "RON", nlconst.one());
m_ROFF = new param_fp_t(this, "ROFF", nlconst.magic(1.0E20));
m_R = new analog.nld_R_base(this, "_R");
m_I = new logic_input_t(this, "I", input);
m_last_state = new state_var <netlist_sig_t>(this, "m_last_state", 0);
register_subalias("1", "_R.1");
register_subalias("2", "_R.2");
}
//NETLIB_CONSTRUCTOR(7448)
public nld_7448(object owner, string name)
: base(owner, name)
{
m_A = new logic_input_t(this, "A", inputs);
m_B = new logic_input_t(this, "B", inputs);
m_C = new logic_input_t(this, "C", inputs);
m_D = new logic_input_t(this, "D", inputs);
m_LTQ = new logic_input_t(this, "LTQ", inputs);
m_BIQ = new logic_input_t(this, "BIQ", inputs);
m_RBIQ = new logic_input_t(this, "RBIQ", inputs);
m_state = new state_var <unsigned>(this, "m_state", 0);
m_Q = new object_array_t_logic_output_t <u64_const_7>(this, new logic_output_t(this, "a"), new logic_output_t(this, "b"), new logic_output_t(this, "c"), new logic_output_t(this, "d"), new logic_output_t(this, "e"), new logic_output_t(this, "f"), new logic_output_t(this, "g"));
m_power_pins = new nld_power_pins(this);
}
state_var <D> m_dis; //state_var<distribution> m_dis;
//NETLIB_CONSTRUCTOR(sys_noise)
//detail.family_setter_t m_famsetter;
//template <class CLASS>
public nld_sys_noise(object owner, string name)
: base(owner, name)
{
m_T = new analog.nld_twoterm(this, "m_T");
m_I = new logic_input_t(this, "I", input);
m_RI = new param_fp_t(this, "RI", nlconst.magic(0.1));
m_sigma = new param_fp_t(this, "SIGMA", nlconst.zero());
m_mt = new state_var <E>(this, "m_mt");
m_dis = new state_var <D>(this, "m_dis", ops.new_(m_sigma.op()));
register_subalias("1", "m_T.1");
register_subalias("2", "m_T.2");
}
//NETLIB_CONSTRUCTOR(7490)
public nld_7490(object owner, string name)
: base(owner, name)
{
m_A = new logic_input_t(this, "A", inputs);
m_B = new logic_input_t(this, "B", inputs);
m_R1 = new logic_input_t(this, "R1", inputs);
m_R2 = new logic_input_t(this, "R2", inputs);
m_R91 = new logic_input_t(this, "R91", inputs);
m_R92 = new logic_input_t(this, "R92", inputs);
m_cnt = new state_var_u8(this, "m_cnt", 0);
m_last_A = new state_var <netlist_sig_t>(this, "m_last_A", 0);
m_last_B = new state_var <netlist_sig_t>(this, "m_last_B", 0);
m_Q = new object_array_t_logic_output_t <u64_const_4>(this, new logic_output_t(this, "QA"), new logic_output_t(this, "QB"), new logic_output_t(this, "QC"), new logic_output_t(this, "QD"));
m_power_pins = new nld_power_pins(this);
}
public nld_d_to_a_proxy(netlist_state_t anetlist, string name, logic_output_t out_proxied)
: base(anetlist, name, out_proxied)
{
m_I = new logic_input_t(this, "I", input);
m_RP = new analog.nld_twoterm(this, "RP");
m_RN = new analog.nld_twoterm(this, "RN");
m_last_state = new state_var <netlist_sig_t>(this, "m_last_var", terminal_t.OUT_TRISTATE());
register_subalias("Q", "RN.1");
connect(m_RN.N(), m_tn);
connect(m_RP.P(), m_tp);
connect(m_RN.P(), m_RP.N());
}
// ----------------------------------------------------------------------------------------
// matrix_solver
// ----------------------------------------------------------------------------------------
protected matrix_solver_t(netlist_base_t anetlist, string name, eSortType sort, solver_parameters_t params_)
: base(anetlist, name)
{
m_params = params_;
m_stat_calculations = new state_var <int>(this, "m_stat_calculations", 0);
m_stat_newton_raphson = new state_var <int>(this, "m_stat_newton_raphson", 0);
m_stat_vsolver_calls = new state_var <int>(this, "m_stat_vsolver_calls", 0);
m_iterative_fail = new state_var <int>(this, "m_iterative_fail", 0);
m_iterative_total = new state_var <int>(this, "m_iterative_total", 0);
m_last_step = new state_var <netlist_time>(this, "m_last_step", netlist_time.zero());
m_fb_sync = new logic_input_t(this, "FB_sync");
m_Q_sync = new logic_output_t(this, "Q_sync");
m_ops = 0;
m_sort = sort;
connect_post_start(m_fb_sync, m_Q_sync);
}
//NETLIB_CONSTRUCTOR(9316_base)
public nld_9316_base(object owner, string name, desc_base desc)
: base(owner, name)
{
D = desc;
m_CLK = new logic_input_t(this, "CLK", clk);
m_ENT = new logic_input_t(this, "ENT", other);
m_LOADQ = new logic_input_t(this, "LOADQ", other);
m_ENP = new logic_input_t(this, "ENP", other);
m_CLRQ = new logic_input_t(this, "CLRQ", other);
m_ABCD = new object_array_t_logic_input_t <u64_const_4>(this, new logic_input_t(this, "A", abcd), new logic_input_t(this, "B", abcd), new logic_input_t(this, "C", abcd), new logic_input_t(this, "D", abcd));
m_RC = new logic_output_t(this, "RC");
m_Q = new object_array_t_logic_output_t <u64_const_4>(this, new logic_output_t(this, "QA"), new logic_output_t(this, "QB"), new logic_output_t(this, "QC"), new logic_output_t(this, "QD"));
m_cnt = new state_var <unsigned>(this, "m_cnt", 0);
m_abcd = new state_var <unsigned>(this, "m_abcd", 0);
m_loadq = new state_var <unsigned>(this, "m_loadq", 0);
m_ent = new state_var <unsigned>(this, "m_ent", 0);
m_power_pins = new nld_power_pins(this);
}
public void remove_from_active_list(core_terminal_t term)
{
//throw new emu_unimplemented();
#if false
gsl_Expects(!m_list_active.empty());
#endif
m_list_active.remove(term);
if (m_list_active.empty())
{
#if (AVOID_NOOP_QUEUE_PUSHES)
if (!!is_queued())
{
exec().qremove(this);
m_in_queue = queue_status::DELAYED_DUE_TO_INACTIVE;
}
#endif
railterminal().device().do_dec_active();
}
}
//NETLIB_CONSTRUCTOR(QBJT_switch)
public nld_QBJT_switch(object owner, string name)
: base(owner, name)
{
m_modacc = new bjt_model_t(m_model);
m_RB = new nld_twoterm(this, "m_RB", termhandler);
m_RC = new nld_twoterm(this, "m_RC", termhandler);
m_BC = new nld_twoterm(this, "m_BC", termhandler);
m_gB = nlconst.cgmin();
m_gC = nlconst.cgmin();
m_V = nlconst.zero();
m_state_on = new state_var <unsigned>(this, "m_state_on", 0U);
register_subalias("B", m_RB.P());
register_subalias("E", m_RB.N());
register_subalias("C", m_RC.P());
connect(m_RB.N(), m_RC.N());
connect(m_RB.P(), m_BC.P());
connect(m_RC.P(), m_BC.N());
}
public generic_diode(diode_e TYPE_, core_device_t dev, string name)
{
TYPE = TYPE_;
m_Vd = new state_var <nl_fptype>(dev, name + ".m_Vd", nlconst.diode_start_voltage());
m_Id = new state_var <nl_fptype>(dev, name + ".m_Id", nlconst.zero());
m_G = new state_var <nl_fptype>(dev, name + ".m_G", nlconst.cgminalt());
m_Vt = nlconst.zero();
m_Vmin = nlconst.zero(); // not used in MOS model
m_Is = nlconst.zero();
m_logIs = nlconst.zero();
m_gmin = nlconst.cgminalt();
m_VtInv = nlconst.zero();
m_Vcrit = nlconst.zero();
set_param(
nlconst.np_Is()
, nlconst.one()
, nlconst.cgminalt()
, nlconst.T0());
//m_name = name;
}
public void add_to_active_list(core_terminal_t term)
{
if (!m_list_active.empty())
{
term.set_copied_input(m_cur_Q.op);
m_list_active.push_front(term);
}
else
{
m_list_active.push_front(term);
railterminal().device().do_inc_active();
if (m_in_queue.op == queue_status.DELAYED_DUE_TO_INACTIVE)
{
#if (AVOID_NOOP_QUEUE_PUSHES)
if (m_next_scheduled_time > exec().time() &&
(m_cur_Q != m_new_Q))
#else
if (m_next_scheduled_time.op > exec().time())
#endif
{
m_in_queue.op = queue_status.QUEUED; // pending
exec().qpush(new plib.pqentry_t <netlist_time, net_t>(m_next_scheduled_time.op, this));
}
else
{
m_in_queue.op = queue_status.DELIVERED;
m_cur_Q = m_new_Q;
}
update_inputs();
}
else
{
term.set_copied_input(m_cur_Q.op);
}
}
}
//NETLIB_HANDLERI(inputs)
void inputs()
{
// FIXME: assumes GND is connected to 0V.
var reset = m_RESET.op();
nl_fptype vthresh = clamp_hl(m_R2.P().op(), nlconst.magic(0.7), nlconst.magic(1.4));
nl_fptype vtrig = clamp_hl(m_R2.N().op(), nlconst.magic(0.7), nlconst.magic(1.4));
// avoid artificial oscillation due to overshoot compensation when
// the control input is used.
var ovlimit = std.min(m_ovlimit, std.max(0.0, (vthresh - vtrig) / 3.0));
if (reset == 0 && m_last_reset.op)
{
m_ff.op = false;
}
else
{
#if (NL_USE_BACKWARD_EULER)
bool bthresh = (m_THRES.op() + m_overshoot.op > vthresh);
bool btrig = (m_TRIG.op() - m_overshoot.op > vtrig);
#else
const bool bthresh = (m_THRES() + m_overshoot > vthresh);
const bool btrig = (m_TRIG() - m_undershoot > vtrig);
#endif
if (!btrig)
{
m_ff.op = true;
}
else if (bthresh)
{
m_ff.op = false;
}
}
bool out_ = (reset == 0 ? false : m_ff.op);
if (m_last_out.op && !out_)
{
#if (NL_USE_BACKWARD_EULER)
m_overshoot.op += ((m_THRES.op() - vthresh)) * 2.0;
#else
m_overshoot += ((m_THRES() - vthresh));
#endif
m_overshoot.op = plib.pg.clamp(m_overshoot.op, nlconst.zero(), ovlimit);
//if (this->name() == "IC6_2")
// printf("%f %s %f %f %f\n", exec().time().as_double(), this->name().c_str(), m_overshoot(), m_R2.P()(), m_THRES());
m_RDIS.change_state(() =>
{
m_RDIS.set_R(nlconst.magic(R_ON));
});
m_OUT.push(m_R3.N().op());
}
else if (!m_last_out.op && out_)
{
#if (NL_USE_BACKWARD_EULER)
m_overshoot.op += (vtrig - m_TRIG.op()) * 2.0;
m_overshoot.op = plib.pg.clamp(m_overshoot.op, nlconst.zero(), ovlimit);
#else
m_undershoot += (vtrig - m_TRIG());
m_undershoot = plib::clamp(m_undershoot(), nlconst::zero(), ovlimit);
#endif
m_RDIS.change_state(() =>
{
m_RDIS.set_R(nlconst.magic(R_OFF));
});
// FIXME: Should be delayed by 100ns
m_OUT.push(m_R1.P().op());
}
m_last_reset.op = reset != 0;
m_last_out.op = out_;
}
// Basic math
//
// I(V) = f(V)
//
// G(V) = df/dV(V)
//
// Ieq(V) = I(V) - V * G(V)
//
//
public void update_diode(nl_fptype nVd)
{
if (TYPE == diode_e.BIPOLAR)
{
#if USE_TEXTBOOK_DIODE
if (nVd > m_Vcrit)
{
// if the old voltage is less than zero and new is above
// make sure we move enough so that matrix and current
// changes.
const nl_fptype old = std::max(nlconst::zero(), m_Vd());
const nl_fptype d = std::min(+fp_constants <nl_fptype>::DIODE_MAXDIFF(), nVd - old);
const nl_fptype a = plib::abs(d) * m_VtInv;
m_Vd = old + plib::signum(d) * plib::log1p(a) * m_Vt;
}
else
{
m_Vd = std::max(-fp_constants <nl_fptype>::DIODE_MAXDIFF(), nVd);
}
if (m_Vd < m_Vmin)
{
m_G = m_gmin;
m_Id = -m_Is;
}
else
{
const auto IseVDVt = plib::exp(m_logIs + m_Vd * m_VtInv);
m_Id = IseVDVt - m_Is;
m_G = IseVDVt * m_VtInv + m_gmin;
}
#else
//printf("%s: %g %g\n", m_name.c_str(), nVd, (nl_fptype) m_Vd);
m_Vd.op = nVd;
if (nVd > m_Vcrit)
{
m_Id.op = m_Icrit_p_Is - m_Is + (m_Vd.op - m_Vcrit) * m_Icrit_p_Is * m_VtInv;
m_G.op = m_Icrit_p_Is * m_VtInv + m_gmin;
}
else if (m_Vd.op < m_Vmin)
{
m_G.op = m_gmin;
//m_Id = m_Imin + (m_Vd - m_Vmin) * m_gmin;
//m_Imin = m_gmin * m_Vt - m_Is;
m_Id.op = (m_Vd.op - m_Vmin + m_Vt) * m_gmin - m_Is;
}
else
{
var IseVDVt = plib.pg.exp(m_logIs + m_Vd.op * m_VtInv);
m_Id.op = IseVDVt - m_Is;
m_G.op = IseVDVt * m_VtInv + m_gmin;
}
#endif
}
else if (TYPE == diode_e.MOS)
{
m_Vd.op = nVd;
if (nVd < nlconst.zero())
{
m_G.op = m_Is * m_VtInv + m_gmin;
m_Id.op = m_G.op * m_Vd.op;
}
else // log stepping should already be done in mosfet
{
var IseVDVt = plib.pg.exp(std.min(+fp_constants_double.DIODE_MAXVOLT(), m_logIs + m_Vd.op * m_VtInv));
m_Id.op = IseVDVt - m_Is;
m_G.op = IseVDVt * m_VtInv + m_gmin;
}
}
}
matrix_solver_SOR_mat_t(devices.nld_solver main_solver, string name, matrix_solver_t_net_list_t nets, solver_parameters_t params_, size_t size)
: base(main_solver, name, nets, params_, size)
{
m_omega = new state_var <FT>(this, "m_omega", ops.cast(params_.m_gs_sor.op()));
}
