public override void Assemble(CodeGenerator cgen, Instruction ins, BytecodeStream str)
{
if (ins.Operands.Count != 2)
{
cgen.CreateError("{0} does not take {1} arguments!", ins.Name, ins.Operands.Count);
}
else if (!(ins.Operands[0] is TokenRegister) || (!(ins.Operands[1] is TokenRegister) && !(ins.Operands[1] is TokenIntLiteral) && !(ins.Operands[1] is TokenIdentifier)))
{
cgen.CreateError("Unsupported addressing mode for instruction '{0}'", ins.Name);
}
else
{
TokenRegister op1 = ins.Operands[0] as TokenRegister;
Opcode opcode = Opcode.ADD;
if (ins.Operands[1] is TokenRegister)
{
TokenRegister op2 = ins.Operands[1] as TokenRegister;
str.Emit(new QuasarInstruction(opcode, new RegisterOperand(op1.Register), new RegisterOperand(op2.Register)));
}
else if (ins.Operands[1] is TokenIntLiteral)
{
TokenIntLiteral op2 = ins.Operands[1] as TokenIntLiteral;
Console.WriteLine("Add with " + op1.Register);
str.Emit(new QuasarInstruction(opcode, new RegisterOperand(op1.Register), new IntegerOperand((int)op2.Value)));
}
else if (ins.Operands[1] is TokenIdentifier)
{
TokenIdentifier ident = ins.Operands[1] as TokenIdentifier;
str.Emit(new QuasarInstruction(opcode, new RegisterOperand(op1.Register), new SymbolReferenceOperand(ident.Value)));
}
}
}
public override void Assemble(CodeGenerator cgen, Instruction ins, BytecodeStream str)
{
if (ins.Operands.Count != 2)
{
cgen.CreateError("{0} does not take {1} arguments!", ins.Name, ins.Operands.Count);
}
else if (!(ins.Operands[0] is TokenIntLiteral || ins.Operands[0] is TokenRegister) && !(ins.Operands[1] is TokenRegister))
{
cgen.CreateError("Unsupported addressing mode for instruction '{0}'", ins.Name);
}
else
{
TokenRegister op2 = ins.Operands[1] as TokenRegister;
Opcode opcode = Opcode.OUT;
if (ins.Operands[0] is TokenRegister)
{
TokenRegister op1 = ins.Operands[0] as TokenRegister;
str.Emit(new QuasarInstruction(opcode, new RegisterOperand(op1.Register), new RegisterOperand(op2.Register)));
}
else if (ins.Operands[0] is TokenIntLiteral)
{
TokenIntLiteral op1 = ins.Operands[0] as TokenIntLiteral;
str.Emit(new QuasarInstruction(opcode, new IntegerOperand((int)op1.Value), new RegisterOperand(op2.Register)));
}
}
}
public override void Assemble(CodeGenerator cgen, Instruction ins, BytecodeStream str)
{
if (ins.Operands.Count != 1)
{
cgen.CreateError("{0} does not take {1} arguments!", ins.Name, ins.Operands.Count);
}
else if (!(ins.Operands[0] is TokenIntLiteral))
{
cgen.CreateError("Unsupported addressing mode for instruction '{0}'", ins.Name);
}
else
{
TokenIntLiteral il = ins.Operands[0] as TokenIntLiteral;
str.Emit(new OrgDirective((uint)il.Value));
}
}
public override void Assemble(CodeGenerator cgen, Instruction ins, BytecodeStream str)
{
if (ins.Operands.Count != 2)
{
cgen.CreateError("Instruction {0} does not take {1} operand(s)!", ins.Name, ins.Operands.Count);
}
else if (ins.Name == "movb")
{
if (ins.Operands[0] is TokenIndirectRegister &&
ins.Operands[1] is TokenRegister)
{
TokenIndirectRegister r1 = ins.Operands[0] as TokenIndirectRegister;
TokenRegister r2 = ins.Operands[1] as TokenRegister;
str.Emit(new QuasarInstruction(Opcode.MOV, new IndirectRegisterOffsetOperand(r1.Register, AddressingMode.REGISTER_INDIRECT_BYTE, r1.Offset),
new RegisterOperand(r2.Register)));
}
else if (ins.Operands[0] is TokenIndirectRegister &&
ins.Operands[1] is TokenRegister)
{
TokenIndirectRegister r1 = ins.Operands[0] as TokenIndirectRegister;
TokenRegister r2 = ins.Operands[1] as TokenRegister;
str.Emit(new QuasarInstruction(Opcode.MOV, new IndirectRegisterOffsetOperand(r1.Register, AddressingMode.REGISTER_INDIRECT_BYTE, r1.Offset),
new RegisterOperand(r2.Register)));
}
}
else if (ins.Name == "movw")
{
if (ins.Operands[0] is TokenIndirectRegister &&
ins.Operands[1] is TokenRegister)
{
TokenIndirectRegister r1 = ins.Operands[0] as TokenIndirectRegister;
TokenRegister r2 = ins.Operands[1] as TokenRegister;
str.Emit(new QuasarInstruction(Opcode.MOV, new IndirectRegisterOffsetOperand(r1.Register, AddressingMode.REGISTER_INDIRECT_WORD, r1.Offset),
new RegisterOperand(r2.Register)));
}
}
else
{
if (ins.Operands[0] is TokenRegister &&
ins.Operands[1] is TokenRegister)
{
TokenRegister r1 = ins.Operands[0] as TokenRegister;
TokenRegister r2 = ins.Operands[1] as TokenRegister;
str.Emit(new QuasarInstruction(Opcode.MOV, new RegisterOperand(r1.Register),
new RegisterOperand(r2.Register)));
}
else if (ins.Operands[0] is TokenRegister &&
ins.Operands[1] is TokenIntLiteral)
{
TokenRegister r1 = ins.Operands[0] as TokenRegister;
TokenIntLiteral i1 = ins.Operands[1] as TokenIntLiteral;
str.Emit(new QuasarInstruction(Opcode.MOV, new RegisterOperand(r1.Register),
new IntegerOperand((int)i1.Value)));
}
else if (ins.Operands[0] is TokenRegister &&
ins.Operands[1] is TokenIdentifier)
{
TokenRegister r1 = ins.Operands[0] as TokenRegister;
TokenIdentifier i1 = ins.Operands[1] as TokenIdentifier;
str.Emit(new QuasarInstruction(Opcode.MOV, new RegisterOperand(r1.Register),
new SymbolReferenceOperand(i1.Value)));
}
else if (ins.Operands[0] is TokenRegister &&
ins.Operands[1] is TokenIndirectRegister)
{
TokenRegister r1 = ins.Operands[0] as TokenRegister;
TokenIndirectRegister r2 = ins.Operands[1] as TokenIndirectRegister;
str.Emit(new QuasarInstruction(Opcode.MOV, new RegisterOperand(r1.Register),
new IndirectRegisterOffsetOperand(r2.Register, r2.Offset)));
}
else if (ins.Operands[0] is TokenIndirectRegister &&
ins.Operands[1] is TokenRegister)
{
TokenIndirectRegister r1 = ins.Operands[0] as TokenIndirectRegister;
TokenRegister r2 = ins.Operands[1] as TokenRegister;
str.Emit(new QuasarInstruction(Opcode.MOV, new IndirectRegisterOffsetOperand(r1.Register, AddressingMode.REGISTER_INDIRECT, r1.Offset),
new RegisterOperand(r2.Register)));
}
else
{
cgen.CreateError("Unsupported addressing mode for instruction {0}", ins.Name);
}
}
}
