protected void ArithCondSkip(Expression dst, Expression src, Expression cond, FSRIndexedMode indMode, Expression memPtr) { rtlc = RtlClass.ConditionalTransfer; switch (indMode) { case FSRIndexedMode.None: m.Assign(dst, src); m.Branch(cond, SkipToAddr(), rtlc); break; case FSRIndexedMode.INDF: case FSRIndexedMode.PLUSW: m.Assign(dst, src); m.Branch(cond, SkipToAddr(), rtlc); break; case FSRIndexedMode.POSTDEC: m.Assign(dst, src); m.BranchInMiddleOfInstruction(cond, SkipToAddr(), rtlc); m.Assign(memPtr, m.ISub(memPtr, 1)); break; case FSRIndexedMode.POSTINC: m.Assign(dst, src); m.BranchInMiddleOfInstruction(cond, SkipToAddr(), rtlc); m.Assign(memPtr, m.IAdd(memPtr, 1)); break; case FSRIndexedMode.PREINC: m.Assign(memPtr, m.IAdd(memPtr, 1)); m.Assign(dst, src); m.Branch(cond, SkipToAddr(), rtlc); break; } }
private void RewriteBlockInstruction() { var bc = frame.EnsureRegister(Registers.bc); var de = frame.EnsureRegister(Registers.de); var hl = frame.EnsureRegister(Registers.hl); var V = FlagGroup(FlagM.PF); emitter.Assign(emitter.LoadB(de), emitter.LoadB(hl)); emitter.Assign(hl, emitter.IAdd(hl, 1)); emitter.Assign(de, emitter.IAdd(de, 1)); emitter.Assign(bc, emitter.ISub(bc, 1)); emitter.BranchInMiddleOfInstruction(emitter.Ne0(bc), dasm.Current.Address, RtlClass.Transfer); emitter.Assign(V, emitter.Const(PrimitiveType.Bool, 0)); }
private void RewriteB(bool link) { Expression dst; if (Dst.Type == ArmInstructionOperandType.Immediate) { dst = Address.Ptr32((uint)Dst.ImmediateValue.Value); } else { dst = Operand(Dst); } if (link) { rtlc = RtlClass.Transfer | RtlClass.Call; if (instr.ArchitectureDetail.CodeCondition != ArmCodeCondition.AL) { m.BranchInMiddleOfInstruction( TestCond(instr.ArchitectureDetail.CodeCondition).Invert(), Address.Ptr32((uint)(instr.Address + instr.Bytes.Length)), RtlClass.ConditionalTransfer); } m.Call(dst, 0); } else { if (instr.ArchitectureDetail.CodeCondition == ArmCodeCondition.AL) { rtlc = RtlClass.Transfer; m.Goto(dst); } else { rtlc = RtlClass.ConditionalTransfer; var addr = dst as Address; if (addr != null) { m.Branch(TestCond(instr.ArchitectureDetail.CodeCondition), addr, RtlClass.ConditionalTransfer); } else { m.BranchInMiddleOfInstruction( TestCond(instr.ArchitectureDetail.CodeCondition).Invert(), Address.Ptr32((uint)(instr.Address + instr.Bytes.Length)), RtlClass.ConditionalTransfer); m.Goto(dst, RtlClass.Transfer); } } } }
private void MaybeSkip() { if (instr.Condition != Avr32Condition.al) { m.BranchInMiddleOfInstruction(Condition().Invert(), instr.Address + instr.Length, InstrClass.ConditionalTransfer); } }
/// <summary> /// Given an image reader positioned at a Keil sparse switch table, generates /// an <see cref="RtlInstructionCluster" /> that implements the table as a /// sequence of RTL if-instructions. /// </summary> private RtlInstructionCluster MakeCluster(Address addrPatch, ImageReader rdr) { var binder = new StorageBinder(); var areg = binder.EnsureRegister(Registers.A); var m = new RtlEmitter(new List <RtlInstruction>()); while (rdr.TryReadBeUInt16(out ushort uAddrDst)) { if (uAddrDst == 0) { if (!rdr.TryReadBeUInt16(out uAddrDst)) { break; } m.Goto(Address.Ptr16(uAddrDst)); break; } if (!rdr.TryReadByte(out byte bValue)) { break; } var addrDst = Address.Ptr16(uAddrDst); m.BranchInMiddleOfInstruction(m.Eq(areg, bValue), addrDst, InstrClass.ConditionalTransfer); } int length = (int)(rdr.Address - addrPatch); var cluster = m.MakeCluster(addrPatch, length, InstrClass.Transfer); return(cluster); }
private void RewriteBlockInstruction(Func <Expression, Expression, Expression> incdec, bool repeat) { var bc = binder.EnsureRegister(Registers.bc); var de = binder.EnsureRegister(Registers.de); var hl = binder.EnsureRegister(Registers.hl); var V = FlagGroup(FlagM.PF); m.Assign(m.Mem8(de), m.Mem8(hl)); m.Assign(hl, incdec(hl, Constant.Int16(1))); m.Assign(de, incdec(de, Constant.Int16(1))); m.Assign(bc, m.ISub(bc, 1)); if (repeat) { m.BranchInMiddleOfInstruction(m.Ne0(bc), dasm.Current.Address, InstrClass.Transfer); } m.Assign(V, m.Const(PrimitiveType.Bool, 0)); }
private void RewriteJbc() { iclass = InstrClass.ConditionalTransfer; var src = OpSrc(instr.Operands[0]); m.BranchInMiddleOfInstruction(m.Eq0(src), instr.Address + instr.Length, iclass); WriteDst(instr.Operands[0], Constant.Zero(src.DataType)); m.Goto(OpSrc(instr.Operands[1])); }
private void RewriteBlockInstruction(Func <Expression, Expression, Expression> incdec, bool repeat) { var bc = frame.EnsureRegister(Registers.bc); var de = frame.EnsureRegister(Registers.de); var hl = frame.EnsureRegister(Registers.hl); var V = FlagGroup(FlagM.PF); emitter.Assign(emitter.LoadB(de), emitter.LoadB(hl)); emitter.Assign(hl, incdec(hl, Constant.Int16(1))); emitter.Assign(de, incdec(de, Constant.Int16(1))); emitter.Assign(bc, emitter.ISub(bc, 1)); if (repeat) { emitter.BranchInMiddleOfInstruction(emitter.Ne0(bc), dasm.Current.Address, RtlClass.Transfer); } emitter.Assign(V, emitter.Const(PrimitiveType.Bool, 0)); }
private void RewriteBtclr() { var cond = RewriteSrc(instr.Operands[0]); m.BranchInMiddleOfInstruction(m.Not(cond), instr.Address + instr.Length, InstrClass.ConditionalTransfer); RewriteDst(instr.Operands[0], Constant.False(), (a, b) => b); m.Goto(((AddressOperand)instr.Operands[1]).Address); }
private void RewriteJbc() { rtlc = RtlClass.ConditionalTransfer; var src = OpSrc(instr.Operand1); m.BranchInMiddleOfInstruction(m.Eq0(src), instr.Address + instr.Length, rtlc); WriteDst(instr.Operand1, Constant.Zero(src.DataType)); m.Goto(OpSrc(instr.Operand2)); }
private void RewriteCall(HexagonInstruction instr) { if (instr.ConditionPredicate != null) { var pred = RewritePredicateExpression(instr.ConditionPredicate, !instr.ConditionInverted); m.BranchInMiddleOfInstruction(pred, instr.Address + 4, InstrClass.ConditionalTransfer); } m.Call(OperandSrc(instr.Operands[0]) !, 0); }
// If a conditional ARM instruction is encountered, generate an IL // instruction to skip the remainder of the instruction cluster. private void ConditionalSkip() { var cc = instr.ArchitectureDetail.CodeCondition; if (cc == ArmCodeCondition.AL) { return; // never skip! } m.BranchInMiddleOfInstruction( TestCond(cc).Invert(), Address.Ptr32((uint)instr.Address + 4), RtlClass.ConditionalTransfer); }
private void Predicate(ArmCodeCondition cond, RtlInstruction instr) { if (cond == ArmCodeCondition.AL) { m.Emit(instr); } else { m.BranchInMiddleOfInstruction( TestCond(cond).Invert(), Address.Ptr32((uint)(this.instr.Address + this.instr.Bytes.Length)), RtlClass.ConditionalTransfer); m.Emit(instr); } }
private void RewriteSbis() { var io = host.Intrinsic("__in", false, PrimitiveType.Byte, RewriteOp(0)); var bis = host.Intrinsic("__bit_set", true, PrimitiveType.Bool, io, RewriteOp(1)); if (!dasm.MoveNext()) { m.Invalid(); return; } var addrSkip = dasm.Current.Address + dasm.Current.Length; var branch = m.BranchInMiddleOfInstruction(bis, addrSkip, InstrClass.ConditionalTransfer); clusters.Add(m.MakeCluster(this.instr.Address, this.instr.Length, InstrClass.ConditionalTransfer)); Rewrite(dasm.Current); }
private void RewriteSbis() { var io = host.PseudoProcedure("__in", PrimitiveType.Byte, RewriteOp(0)); var bis = host.PseudoProcedure("__bit_set", PrimitiveType.Bool, io, RewriteOp(1)); if (!dasm.MoveNext()) { m.Invalid(); return; } var addrSkip = dasm.Current.Address + dasm.Current.Length; var branch = m.BranchInMiddleOfInstruction(bis, addrSkip, RtlClass.ConditionalTransfer); rtlc.Class = RtlClass.ConditionalTransfer; clusters.Add(rtlc); Rewrite(dasm.Current); }
void CheckForLoopExit() { if (lend == null) { return; } if (instr.Address.ToLinear() + (uint)instr.Length == lend.ToLinear()) { var addrNext = instr.Address + instr.Length; var lcount = binder.EnsureRegister(Registers.LCOUNT); m.BranchInMiddleOfInstruction(m.Eq0(lcount), addrNext, InstrClass.ConditionalTransfer); m.Assign(lcount, m.ISub(lcount, 1)); m.Goto(this.lbegin); lbegin = null; lend = null; } }
private void RewriteBranch(ConditionCode cc) { var reg = Reg(0); var cond = m.Test(cc, reg); if (instrCur.Operands[1] is AddressOperand addrDst) { m.Branch(cond, addrDst.Address, instrCur.InstructionClass); } else { var regDst = Reg(1); m.BranchInMiddleOfInstruction( cond.Invert(), instrCur.Address + instrCur.Length, InstrClass.ConditionalTransfer); m.Goto(m.IAdd(instrCur.Address, regDst)); } }
private void RewriteSbis() { var io = host.PseudoProcedure("__in", PrimitiveType.Byte, RewriteOp(0)); var bis = host.PseudoProcedure("__bit_set", PrimitiveType.Bool, io, RewriteOp(1)); if (!dasm.MoveNext()) { m.Invalid(); return; } var addrSkip = dasm.Current.Address + dasm.Current.Length; var branch = m.BranchInMiddleOfInstruction(bis, addrSkip, InstrClass.ConditionalTransfer); clusters.Add(new RtlInstructionCluster( this.instr.Address, this.instr.Length, this.rtlInstructions.ToArray()) { Class = InstrClass.ConditionalTransfer, }); Rewrite(dasm.Current); }
public void BranchInMiddleOfInstruction(HExpr exp, HExpr dst, InstrClass rtlClass) { m.BranchInMiddleOfInstruction(GetExpression(exp), (Address)GetExpression(dst), rtlClass); }