public void Initialize()
{
cpu.EnablePerformanceCounters();
for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++)
{
ThreadAffinity.Set(1UL << threadIdx);
// MITE uops, cmask 1,2,3,5
Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x79, 0x4, true, true, false, false, false, false, true, false, 1));
Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x79, 0x4, true, true, false, false, false, false, true, false, 2));
Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x79, 0x4, true, true, false, false, false, false, true, false, 4));
Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x79, 0x4, true, true, false, false, false, false, true, false, 5));
}
}
public void Initialize()
{
cpu.EnablePerformanceCounters();
for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++)
{
ThreadAffinity.Set(1UL << threadIdx);
// SQ occupancy, code/data
Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x60, 0x8 | 0x2, true, true, false, false, false, false, true, false, cmask: 0));
// SQ requests
Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xB0, 0x8 | 0x2, true, true, false, false, false, false, true, false, cmask: 0));
// SQ Full
Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xB2, 0x1, true, true, false, false, false, false, true, false, 0));
// SQ occupancy cmask 16
Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x60, 0x8 | 0x2, true, true, false, false, false, false, true, false, 16));
}
}
