private void Inst_Addi(MipsInstruction inst)
{
if (!MipsState.Operating64BitMode)
{
try
{
MipsState.WriteGPR32Signed(inst.Rt, MipsState.ReadGPR32Signed(inst.Rs) + (Int32)(Int16)inst.Immediate);
}
catch (OverflowException)
{
CauseException = ExceptionCode.OverFlow;
}
}
else
{
try
{
MipsState.WriteGPRSigned(inst.Rt, MipsState.ReadGPRSigned(inst.Rs) + (Int64)(Int16)inst.Immediate);
}
catch (OverflowException)
{
CauseException = ExceptionCode.OverFlow;
}
}
}
private void Inst_Add(MipsInstruction inst)
{
if (!MipsState.Operating64BitMode)
{
try
{
MipsState.WriteGPR32Signed(inst.Rd, MipsState.ReadGPR32Signed(inst.Rs) + MipsState.ReadGPR32Signed(inst.Rt));
}
catch (OverflowException)
{
CauseException = ExceptionCode.OverFlow;
}
}
else
{
if (MipsState.ReadGPRUnsigned(inst.Rs).IsSigned32() && MipsState.ReadGPRUnsigned(inst.Rt).IsSigned32())
{
try
{
MipsState.WriteGPRSigned(inst.Rd, MipsState.ReadGPRSigned(inst.Rs) + MipsState.ReadGPRSigned(inst.Rt));
}
catch (OverflowException)
{
CauseException = ExceptionCode.OverFlow;
}
}
}
}
private void Inst_Lh(MipsInstruction inst)
{
try
{
Int64 address = ComputeAddress(inst);
if ((address & 3) != 0)
{
CauseException = ExceptionCode.AddressErrorLoad;
return;
}
if (!MipsState.Operating64BitMode)
{
MipsState.WriteGPR32Signed(inst.Rt, DataManipulator.LoadHalfwordSigned(address));
}
else
{
MipsState.WriteGPRSigned(inst.Rt, DataManipulator.LoadHalfwordSigned(address));
}
}
catch (TLBException tlbe)
{
switch (tlbe.ExceptionType)
{
case TLBExceptionType.Invalid: CauseException = ExceptionCode.Invalid; break;
case TLBExceptionType.Mod: CauseException = ExceptionCode.TlbMod; break;
case TLBExceptionType.Refill: CauseException = ExceptionCode.TlbStore; break;
default: break;
}
}
}
private void Inst_Lbu(MipsInstruction inst)
{
try
{
if (!MipsState.Operating64BitMode)
{
MipsState.WriteGPR32Signed(inst.Rt, DataManipulator.LoadByteUnsigned(ComputeAddress(inst)));
}
else
{
MipsState.WriteGPRSigned(inst.Rt, DataManipulator.LoadByteUnsigned(ComputeAddress(inst)));
}
}
catch (TLBException tlbe)
{
switch (tlbe.ExceptionType)
{
case TLBExceptionType.Invalid: CauseException = ExceptionCode.Invalid; break;
case TLBExceptionType.Mod: CauseException = ExceptionCode.TlbMod; break;
case TLBExceptionType.Refill: CauseException = ExceptionCode.TlbStore; break;
default: break;
}
}
}
private void Inst_Xori(MipsInstruction inst)
{
if (!MipsState.Operating64BitMode)
{
MipsState.WriteGPR32Signed(inst.Rt, MipsState.ReadGPR32Signed(inst.Rs) ^ (Int32)(Int16)inst.Immediate);
}
else
{
MipsState.WriteGPRSigned(inst.Rt, MipsState.ReadGPRSigned(inst.Rs) ^ (Int64)(Int16)inst.Immediate);
}
}
private void Inst_Sub(MipsInstruction inst)
{
try
{
MipsState.WriteGPR32Signed(inst.Rd, MipsState.ReadGPR32Signed(inst.Rs) - MipsState.ReadGPR32Signed(inst.Rt));
}
catch (OverflowException)
{
CauseException = ExceptionCode.OverFlow;
}
}
private void Inst_Srav(MipsInstruction inst)
{
Int32 result = MipsState.ReadGPR32Signed(inst.Rt) >> (MipsState.ReadGPR32Signed(inst.Rs) & 0x1F);
if (!MipsState.Operating64BitMode)
{
MipsState.WriteGPR32Signed(inst.Rd, result);
}
else
{
MipsState.WriteGPRSigned(inst.Rd, result);
}
}
private void Inst_Sra(MipsInstruction inst)
{
Int32 result = MipsState.ReadGPR32Signed(inst.Rt) >> inst.ShiftAmount;
if (!MipsState.Operating64BitMode)
{
MipsState.WriteGPR32Signed(inst.Rd, result);
}
else
{
MipsState.WriteGPRSigned(inst.Rd, result);
}
}
private void Inst_Lw(MipsInstruction inst)
{
Int64 address = ComputeAddress(inst);
if ((address & 3) != 0)
{
CauseException = ExceptionCode.AddressErrorLoad;
}
else
{
if (!MipsState.Operating64BitMode)
{
MipsState.WriteGPR32Signed(inst.Rt, DataManipulator.LoadWordSigned(address));
}
else
{
MipsState.WriteGPRSigned(inst.Rt, DataManipulator.LoadWordSigned(address));
}
}
}