public PARBS(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
_rank = new int[Config.N];
_markedMaxLoadPerProc = new uint[Config.N];
_markedTotalLoadPerProc = new uint[Config.N];
}
public MemSched(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
{
Mctrl = mctrl;
Mctrls = mctrls;
LocalBcount = mctrl.Rmax * mctrl.Bmax;
GlobalBcount = (uint)mctrls.Length * LocalBcount;
}
public ATLAS(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
_rank = new int[Config.N];
_serviceBankCnt = new uint[Config.N];
_currService = new double[Config.N];
_service = new double[Config.N];
_quantumCyclesLeft = Config.sched.quantum_cycles;
}
public FRFCFS_SACAP(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
streak = new int[mctrl.Rmax, mctrl.Bmax, mctrl.ddr3.SUBARRAYS_PER_BANK];
for (int r = 0; r < mctrl.Rmax; r++)
{
for (int b = 0; b < mctrl.Bmax; b++)
{
for (int s = 0; s < mctrl.ddr3.SUBARRAYS_PER_BANK; s++)
{
streak[r, b, s] = 0;
}
}
}
}
public TCM(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
_rank = new int[Config.N];
_service = new double[Config.N];
_currService = new double[Config.N];
_serviceBankCnt = new uint[Config.N];
_mpki = new double[Config.N];
_prevCacheMiss = new ulong[Config.N];
_prevInstCnt = new ulong[Config.N];
_rbl = new double[Config.N];
_shadowRowHits = new ulong[Config.N];
_blp = new double[Config.N];
_blpSampleSum = new uint[Config.N];
_quantumCyclesLeft = Config.sched.quantum_cycles;
_nice = new int[Config.N];
_shuffleCyclesLeft = Config.sched.shuffle_cycles;
}
public void Initialize()
{
Stat = new Stat();
// Crossbar
Xbar = new Xbar();
// ddr3
DDR3DRAM ddr3 = new DDR3DRAM(Config.mem.ddr3_type,
Config.mem.clock_factor, Config.mem.tRTRS, Config.mem.tWR,
Config.mem.tWTR, Config.mem.tBL, Config.mem.bank_max,
Config.mem.subarray_max, Config.mem.col_max,
Config.mem.tRA, Config.mem.tWA, Config.mem.tREFI,
Config.mem.tRFC, Config.mem.tRP, Config.mem.tRCD);
uint cmax = Config.mem.chan_max;
uint rmax = Config.mem.rank_max;
// randomized page table
const ulong page_size = 4 * 1024;
PageRandomizer prand = new PageRandomizer(page_size, ddr3.ROW_MAX);
Req.Prand = prand;
// sequential page table
PageSequencer pseq = new PageSequencer(page_size, cmax, rmax, ddr3.BANK_MAX);
Req.Pseq = pseq;
// Contiguous physical page allocation
ContiguousAllocator pcontig = new ContiguousAllocator(page_size, cmax * rmax * ddr3.ROW_MAX * ddr3.DEVICE_WIDTH);
Req.Pcontig = pcontig;
// memory mapping
MemMap.Init(Config.mem.map_type, Config.mem.chan_max, Config.mem.rank_max, Config.mem.col_per_subrow, ddr3);
// Cache hierarchy
if (Config.proc.cache_enabled)
{
Caches = new CacheHierarchy(Config.N);
}
// processors
Procs = new Proc.Proc[Config.N];
for (int p = 0; p < Config.N; p++)
{
Procs[p] = new Proc.Proc(Config.traceFileNames[p], Caches);
}
// memory controllers
Mctrls = new MemCtrl.MemCtrl[cmax];
for (int i = 0; i < Mctrls.Length; i++)
{
Mctrls[i] = new MemCtrl.MemCtrl(rmax, ddr3);
// Add ref handles to processors
for (int p = 0; p < Config.N; p++)
{
Procs[p].mctrls[i] = Mctrls[i];
Mctrls[i].ProcHandles[p] = Procs[p];
}
}
// memory schedulers
MemSched.MemSched[] rscheds = new MemSched.MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
Object[] args = { Mctrls[i], Mctrls };
rscheds[i] = Activator.CreateInstance(Config.sched.typeof_sched_algo, args) as MemSched.MemSched;
}
MemSched.MemSched[] wscheds = new MemSched.MemSched[cmax];
for (int i = 0; i < cmax; i++)
{
Object[] args = { Mctrls[i], Mctrls };
wscheds[i] = Activator.CreateInstance(Config.sched.typeof_wbsched_algo, args) as MemSched.MemSched;
}
for (int i = 0; i < cmax; i++)
{
Mctrls[i].Rsched = rscheds[i];
Mctrls[i].Wsched = wscheds[i];
rscheds[i].Initialize();
wscheds[i].Initialize();
}
// WB mode
Mwbmode = Activator.CreateInstance(Config.mctrl.typeof_wbmode_algo, new Object[] { Mctrls }) as MemWBMode.MemWBMode;
for (int i = 0; i < cmax; i++)
{
Mctrls[i].Mwbmode = Mwbmode;
}
// BLP tracker
Blptracker = new BLPTracker(Mctrls);
}
public DRAMState(uint cid, uint[] fanOutArray, MemCtrl.MemCtrl mctrl)
{
_channel = new NodeMachine(null, 0, cid, fanOutArray);
}
public FCFS(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
}
protected bool is_readq_empty(uint cid)
{
MemCtrl.MemCtrl mctrl = Mctrls[cid];
return(mctrl.Rload == 0);
}
protected bool is_writeq_full(uint cid)
{
MemCtrl.MemCtrl mctrl = Mctrls[cid];
return(mctrl.Wload == mctrl.WriteqMax);
}
protected bool is_writeq_empty(uint cid)
{
MemCtrl.MemCtrl mctrl = Mctrls[cid];
return(mctrl.Wload == 0);
}
public BLISS(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
_shuffleCyclesLeft = Config.sched.bliss_shuffle_cycles;
_mark = new int[Config.N];
}
public FRFCFS_CAP(MemCtrl.MemCtrl mctrl, MemCtrl.MemCtrl[] mctrls)
: base(mctrl, mctrls)
{
}
