protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
var hasExtension = ExecutionEngine.Opcode.Definition.HasExtension;
switch (machineCycle)
{
case MachineCycleNames.M2:
if (!hasExtension)
{
return(CreateWriteAddressInstructionPart(machineCycle));
}
return(base.GetInstructionPart(machineCycle));
case MachineCycleNames.M3:
if (!hasExtension)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
// z80 does the IX+d arithemtic
return(new AutoCompleteInstructionPart(Die, machineCycle));
case MachineCycleNames.M4:
if (!hasExtension)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
return(CreateWriteAddressInstructionPart(machineCycle));
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Cpu, machineCycle, Registers.SP);
return(_instructionM2);
case MachineCycleNames.M3:
_instructionM3 = new ReadT3InstructionPart(Cpu, machineCycle, (ushort)(Registers.SP + 1));
return(_instructionM3);
case MachineCycleNames.M4:
return(new WriteT3InstructionPart(Cpu, machineCycle, Registers.SP)
{
Data = new OpcodeByte(GetValueLo())
});
case MachineCycleNames.M5:
return(new WriteT3InstructionPart(Cpu, machineCycle, (ushort)(Registers.SP + 1))
{
Data = new OpcodeByte(GetValueHi())
});
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
// read d
_instructionM2 = new ReadT3InstructionPart(Cpu, machineCycle);
return(_instructionM2);
case MachineCycleNames.M3:
// we postpone inc/dec operation until M4
return(new AutoCompleteInstructionPart(Cpu, machineCycle));
case MachineCycleNames.M4:
_instructionM4 = new ReadT3InstructionPart(Cpu, machineCycle, GetAddress());
return(_instructionM4);
case MachineCycleNames.M5:
_instructionM5 = new WriteT3InstructionPart(Cpu, machineCycle, GetAddress());
_instructionM5.Data = IncDecValue(_instructionM4.Data);
return(_instructionM5);
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M3:
if (IsHL)
{
return new WriteT3InstructionPart(Die, machineCycle, Registers.HL)
{
Data = InstructionM2.Data
}
}
;
break; // another param
case MachineCycleNames.M4:
if (IsHL)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
return(new WriteT3InstructionPart(Die, machineCycle, GetAddress())
{
Data = InstructionM3.Data
});
case MachineCycleNames.M5:
case MachineCycleNames.M6:
throw Errors.InvalidMachineCycle(machineCycle);
}
return(base.GetInstructionPart(machineCycle));
}
private CpuState CreateInputPart(MachineCycleNames machineCycle)
{
DecrementCount();
_inputPart = new InputInstructionPart(Cpu, machineCycle, Registers.BC);
return(_inputPart);
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
var isED = ExecutionEngine.Opcode.Definition.Ext1 == 0xED;
switch (machineCycle)
{
case MachineCycleNames.M2:
return(CreateReadAddressInstructionPart(machineCycle));
case MachineCycleNames.M3:
if (!isED)
{
return(CreateWriteAddressInstructionPart(machineCycle));
}
// z80 computes
return(new AutoCompleteInstructionPart(Cpu, machineCycle));
case MachineCycleNames.M4:
if (!isED)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
return(CreateWriteAddressInstructionPart(machineCycle));
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M4:
return(new WriteT3InstructionPart(Cpu, machineCycle, GetAddress())
{
Data = new OpcodeByte(GetValueLo())
});
case MachineCycleNames.M5:
var regA = ExecutionEngine.Opcode.Definition.P == 3;
if (regA)
{
throw Errors.AssignedToIllegalOpcode();
}
return(new WriteT3InstructionPart(Cpu, machineCycle, (ushort)(GetAddress() + 1))
{
Data = new OpcodeByte(GetValueHi())
});
}
return(base.GetInstructionPart(machineCycle));
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
if (!ExecutionEngine.Opcode.Definition.HasParameters)
{
throw Errors.NoParameters();
}
switch (machineCycle)
{
case MachineCycleNames.M2:
InstructionM2 = new ReadT3InstructionPart(Die, machineCycle);
return(InstructionM2);
case MachineCycleNames.M3:
if (ExecutionEngine.Opcode.Definition.ParameterCount <= 1)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
InstructionM3 = new ReadT3InstructionPart(Die, machineCycle);
return(InstructionM3);
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
private WriteT3InstructionPart CreateWriteAddressInstructionPart(MachineCycleNames machineCycle)
{
_writePart = new WriteT3InstructionPart(Cpu, machineCycle, GetAddress())
{
Data = new OpcodeByte(GetValueToWriteBack(GetValue()))
};
return(_writePart);
}
private CpuState CreateWriteDatatPart(MachineCycleNames machineCycle)
{
_writePart = new Instructions.WriteT3InstructionPart(Die, machineCycle, Registers.DE)
{
Data = _readPart.Data
};
return(_writePart);
}
private CpuState CreateOutputPart(MachineCycleNames machineCycle)
{
_outputPart = new OutputInstructionPart(Die, machineCycle, GetAddress())
{
Data = new OpcodeByte(GetValue())
};
return(_outputPart);
}
private CpuState CreateWriteDataPart(MachineCycleNames machineCycle)
{
_writePart = new WriteT3InstructionPart(Cpu, machineCycle, Registers.HL)
{
Data = _inputPart.Data
};
return(_writePart);
}
private WriteT3InstructionPart CreateWriteAddressInstructionPart(MachineCycleNames machineCycle)
{
_writePart = new WriteT3InstructionPart(Cpu, machineCycle, GetAddress())
{
Data = new OpcodeByte(DoShiftRotate(_readPart.Data.Value))
};
return(_writePart);
}
private CpuState CreateOutputPart(MachineCycleNames machineCycle)
{
_outputPart = new OutputInstructionPart(Cpu, machineCycle, Registers.BC)
{
Data = _readPart.Data
};
return(_outputPart);
}
private CycleNames GetCycle(MachineCycleNames machineCycle)
{
if (_opcodeCycles != null)
{
var index = MachineCycleToIndex(machineCycle);
return((CycleNames)_opcodeCycles[(int)index]);
}
return(CycleNames.NotInitialized);
}
private CpuState CreateOutputPart(MachineCycleNames machineCycle)
{
// decremented B is the IO address MSB
MoveNext();
_outputPart = new OutputInstructionPart(Die, machineCycle, Registers.BC)
{
Data = _readPart.Data
};
return(_outputPart);
}
public RepeatInstructionPart(CpuZ80 cpu, MachineCycleNames activeMachineCycle, sbyte deltaPC)
: base(cpu, activeMachineCycle)
{
if (deltaPC >= 0)
{
throw new ArgumentException(
"The value must be negative.", "deltaPC");
}
_deltaPC = deltaPC;
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M3:
// just chews thru the M3 cycles.
return(new AutoCompleteInstructionPart(Cpu, machineCycle));
default:
return(base.GetInstructionPart(machineCycle));
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
return(CreateReadAddressInstructionPart(machineCycle));
case MachineCycleNames.M3:
return(CreateWriteAddressInstructionPart(machineCycle));
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
private int MachineCycleToIndex(MachineCycleNames machineCycle)
{
int index = (int)machineCycle;
index += _continueCount;
if (index >= _opcodeCycles.Length)
{
throw new InvalidOperationException(
string.Format("The instuction {0} did not signal complete within its declared machine cycles.", OpcodeDefinition));
}
return(index);
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Die, machineCycle, Registers.SP);
return(_instructionM2);
case MachineCycleNames.M3:
_instructionM3 = new ReadT3InstructionPart(Die, machineCycle, Registers.SP);
return(_instructionM3);
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
Registers.SP--;
return(CreateInstructionPartM2());
case MachineCycleNames.M3:
Registers.SP--;
return(CreateInstructionPartM3());
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
case MachineCycleNames.M3:
return(base.GetInstructionPart(machineCycle));
case MachineCycleNames.M4:
return(CreateInstructionPartM4());
case MachineCycleNames.M5:
return(CreateInstructionPartM5());
}
throw Errors.InvalidMachineCycle(machineCycle);
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Cpu, machineCycle, GetAddress());
return(_instructionM2);
case MachineCycleNames.M3:
_instructionM3 = new WriteT3InstructionPart(Cpu, machineCycle, GetAddress());
_instructionM3.Data = IncDecValue(_instructionM2.Data);
return(_instructionM3);
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
private int MachineCycleToIndex(MachineCycleNames machineCycle)
{
int index = (int)machineCycle;
index += _continueCount;
//if (OpcodeDefinition != null &&
// OpcodeDefinition.Ext1 != 0)
//{
// index++;
// if (OpcodeDefinition.Ext2 != 0)
// index++;
//}
return(index);
}
private CycleNames GetCycle(MachineCycleNames machineCycle)
{
if (_opcodeCycles != null)
{
var index = MachineCycleToIndex(machineCycle);
if (index >= _opcodeCycles.Length)
{
throw new InvalidOperationException(
string.Format("The instuction {0} did not signal complete within its declared machine cycles.", OpcodeDefinition));
}
return((CycleNames)_opcodeCycles[(int)index]);
}
return(CycleNames.NotInitialized);
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
var regA = ExecutionEngine.Opcode.Definition.P == 3;
switch (machineCycle)
{
case MachineCycleNames.M4:
_instructionM4 = new ReadT3InstructionPart(Die, machineCycle, GetAddress());
return(_instructionM4);
case MachineCycleNames.M5:
if (regA)
{
throw Errors.AssignedToIllegalOpcode();
}
_instructionM5 = new ReadT3InstructionPart(Die, machineCycle, (ushort)(GetAddress() + 1));
return(_instructionM5);
}
return(base.GetInstructionPart(machineCycle));
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
return(CreateReadDataPart(machineCycle));
case MachineCycleNames.M3:
return(CreateOutputPart(machineCycle));
case MachineCycleNames.M4:
if (!IsRepeat)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
return(CreateRepeatPart(machineCycle));
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
return(CreateReadDataPart(machineCycle));
case MachineCycleNames.M3:
// z80 does computation
return(new AutoCompleteInstructionPart(Cpu, machineCycle));
case MachineCycleNames.M4:
if (!IsRepeat)
{
throw Errors.InvalidMachineCycle(machineCycle);
}
return(CreateRepeatPart(machineCycle));
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Die, machineCycle, _address);
return(_instructionM2);
case MachineCycleNames.M3:
if (IsBitInstruction)
{
throw Errors.AssignedToIllegalOpcode();
}
return(new WriteT3InstructionPart(Die, machineCycle, _address)
{
Data = new OpcodeByte(GetValue())
});
default:
throw Errors.AssignedToIllegalOpcode();
}
}