public InstructionDef(EnumValue code, string opCodeString, string instructionString, EnumValue mnemonic,
EnumValue mem, EnumValue bcst, EnumValue decoderOption, InstructionDefFlags1 flags1, InstructionDefFlags2 flags2,
InstructionDefFlags3 flags3, InstrStrFmtOption instrStrFmtOption, InstructionStringFlags instrStrFlags,
InstrStrImpliedOp[] instrStrImpliedOps,
MandatoryPrefix mandatoryPrefix, OpCodeTableKind table, OpCodeL lBit, OpCodeW wBit, uint opCode, int opCodeLength,
int groupIndex, int rmGroupIndex, CodeSize operandSize, CodeSize addressSize, TupleType tupleType, OpCodeOperandKind[] opKinds,
PseudoOpsKind?pseudoOp, EnumValue encoding, EnumValue flowControl, ConditionCode conditionCode,
BranchKind branchKind, RflagsBits read, RflagsBits undefined, RflagsBits written, RflagsBits cleared, RflagsBits set,
EnumValue[] cpuid, OpInfo[] opInfo,
FastFmtInstructionDef fast, FmtInstructionDef gas, FmtInstructionDef intel, FmtInstructionDef masm, FmtInstructionDef nasm)
{
Code = code;
OpCodeString = opCodeString;
InstructionString = instructionString;
Mnemonic = mnemonic;
Memory = mem;
MemoryBroadcast = bcst;
DecoderOption = decoderOption;
EncodingValue = encoding;
Flags1 = flags1;
Flags2 = flags2;
Flags3 = flags3;
InstrStrFmtOption = instrStrFmtOption;
InstrStrFlags = instrStrFlags;
InstrStrImpliedOps = instrStrImpliedOps;
MandatoryPrefix = mandatoryPrefix;
Table = table;
LBit = lBit;
WBit = wBit;
OpCode = opCode;
OpCodeLength = opCodeLength;
GroupIndex = groupIndex;
RmGroupIndex = rmGroupIndex;
TupleType = tupleType;
OperandSize = operandSize;
AddressSize = addressSize;
OpKinds = opKinds;
PseudoOp = pseudoOp;
ControlFlow = flowControl;
ConditionCode = conditionCode;
BranchKind = branchKind;
RflagsRead = read;
RflagsUndefined = undefined;
RflagsWritten = written;
RflagsCleared = cleared;
RflagsSet = set;
RflagsInfo = null;
Cpuid = cpuid;
CpuidInternal = null;
OpInfo = opInfo;
OpInfoEnum = new EnumValue[opInfo.Length];
Fast = fast;
Gas = gas;
Intel = intel;
Masm = masm;
Nasm = nasm;
}
public InstructionFormatter(OpCodeInfo opCode, InstrStrFmtOption fmtOption, StringBuilder sb)
{
this.opCode = opCode;
this.sb = sb;
noVecIndex = false;
swapVecIndex12 = false;
noGprSuffix = false;
startOpIndex = 0;
bnd_count = 0;
r32_count = 0;
r64_count = 0;
r32_index = 0;
r64_index = 0;
k_index = 0;
vec_index = 0;
tmm_index = 0;
bnd_index = 0;
opCount = opCode.OpCount;
opMaskIsK1 = false;
switch (fmtOption)
{
case InstrStrFmtOption.None:
break;
case InstrStrFmtOption.OpMaskIsK1_or_NoGprSuffix:
opMaskIsK1 = true;
noGprSuffix = true;
break;
case InstrStrFmtOption.IncVecIndex:
vec_index++;
break;
case InstrStrFmtOption.NoVecIndex:
noVecIndex = true;
break;
case InstrStrFmtOption.SwapVecIndex12:
swapVecIndex12 = true;
break;
case InstrStrFmtOption.SkipOp0:
startOpIndex = 1;
break;
default:
throw new InvalidOperationException();
}
if ((opCode.Op0Kind == OpCodeOperandKind.k_reg || opCode.Op0Kind == OpCodeOperandKind.kp1_reg) && opCode.OpCount > 2)
{
vec_index++;
}
for (int i = 0; i < opCode.OpCount; i++)
{
switch (opCode.GetOpKind(i))
{
case OpCodeOperandKind.r32_reg:
case OpCodeOperandKind.r32_reg_mem:
case OpCodeOperandKind.r32_rm:
case OpCodeOperandKind.r32_opcode:
case OpCodeOperandKind.r32_vvvv:
r32_count++;
break;
case OpCodeOperandKind.r64_reg:
case OpCodeOperandKind.r64_reg_mem:
case OpCodeOperandKind.r64_rm:
case OpCodeOperandKind.r64_opcode:
case OpCodeOperandKind.r64_vvvv:
r64_count++;
break;
case OpCodeOperandKind.bnd_or_mem_mpx:
case OpCodeOperandKind.bnd_reg:
bnd_count++;
break;
case OpCodeOperandKind.None:
case OpCodeOperandKind.farbr2_2:
case OpCodeOperandKind.farbr4_2:
case OpCodeOperandKind.mem_offs:
case OpCodeOperandKind.mem:
case OpCodeOperandKind.mem_mpx:
case OpCodeOperandKind.mem_mib:
case OpCodeOperandKind.mem_vsib32x:
case OpCodeOperandKind.mem_vsib64x:
case OpCodeOperandKind.mem_vsib32y:
case OpCodeOperandKind.mem_vsib64y:
case OpCodeOperandKind.mem_vsib32z:
case OpCodeOperandKind.mem_vsib64z:
case OpCodeOperandKind.r8_or_mem:
case OpCodeOperandKind.r16_or_mem:
case OpCodeOperandKind.r32_or_mem:
case OpCodeOperandKind.r32_or_mem_mpx:
case OpCodeOperandKind.r64_or_mem:
case OpCodeOperandKind.r64_or_mem_mpx:
case OpCodeOperandKind.mm_or_mem:
case OpCodeOperandKind.xmm_or_mem:
case OpCodeOperandKind.ymm_or_mem:
case OpCodeOperandKind.zmm_or_mem:
case OpCodeOperandKind.k_or_mem:
case OpCodeOperandKind.r8_reg:
case OpCodeOperandKind.r8_opcode:
case OpCodeOperandKind.r16_reg:
case OpCodeOperandKind.r16_reg_mem:
case OpCodeOperandKind.r16_rm:
case OpCodeOperandKind.r16_opcode:
case OpCodeOperandKind.seg_reg:
case OpCodeOperandKind.k_reg:
case OpCodeOperandKind.kp1_reg:
case OpCodeOperandKind.k_rm:
case OpCodeOperandKind.k_vvvv:
case OpCodeOperandKind.mm_reg:
case OpCodeOperandKind.mm_rm:
case OpCodeOperandKind.xmm_reg:
case OpCodeOperandKind.xmm_rm:
case OpCodeOperandKind.xmm_vvvv:
case OpCodeOperandKind.xmmp3_vvvv:
case OpCodeOperandKind.xmm_is4:
case OpCodeOperandKind.xmm_is5:
case OpCodeOperandKind.ymm_reg:
case OpCodeOperandKind.ymm_rm:
case OpCodeOperandKind.ymm_vvvv:
case OpCodeOperandKind.ymm_is4:
case OpCodeOperandKind.ymm_is5:
case OpCodeOperandKind.zmm_reg:
case OpCodeOperandKind.zmm_rm:
case OpCodeOperandKind.zmm_vvvv:
case OpCodeOperandKind.zmmp3_vvvv:
case OpCodeOperandKind.cr_reg:
case OpCodeOperandKind.dr_reg:
case OpCodeOperandKind.tr_reg:
case OpCodeOperandKind.es:
case OpCodeOperandKind.cs:
case OpCodeOperandKind.ss:
case OpCodeOperandKind.ds:
case OpCodeOperandKind.fs:
case OpCodeOperandKind.gs:
case OpCodeOperandKind.al:
case OpCodeOperandKind.cl:
case OpCodeOperandKind.ax:
case OpCodeOperandKind.dx:
case OpCodeOperandKind.eax:
case OpCodeOperandKind.rax:
case OpCodeOperandKind.st0:
case OpCodeOperandKind.sti_opcode:
case OpCodeOperandKind.imm2_m2z:
case OpCodeOperandKind.imm8:
case OpCodeOperandKind.imm8_const_1:
case OpCodeOperandKind.imm8sex16:
case OpCodeOperandKind.imm8sex32:
case OpCodeOperandKind.imm8sex64:
case OpCodeOperandKind.imm16:
case OpCodeOperandKind.imm32:
case OpCodeOperandKind.imm32sex64:
case OpCodeOperandKind.imm64:
case OpCodeOperandKind.seg_rDI:
case OpCodeOperandKind.br16_1:
case OpCodeOperandKind.br32_1:
case OpCodeOperandKind.br64_1:
case OpCodeOperandKind.br16_2:
case OpCodeOperandKind.br32_4:
case OpCodeOperandKind.br64_4:
case OpCodeOperandKind.xbegin_2:
case OpCodeOperandKind.xbegin_4:
case OpCodeOperandKind.brdisp_2:
case OpCodeOperandKind.brdisp_4:
case OpCodeOperandKind.sibmem:
case OpCodeOperandKind.tmm_reg:
case OpCodeOperandKind.tmm_rm:
case OpCodeOperandKind.tmm_vvvv:
break;
case OpCodeOperandKind.seg_rSI:
case OpCodeOperandKind.es_rDI:
case OpCodeOperandKind.seg_rBX_al:
// string instructions, xlat
opCount = 0;
break;
default:
throw new InvalidOperationException();
}
}
}
