protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
StringBuilder buffer = new StringBuilder();
buffer.AppendLine("################ GoAhead ################ GoAhead ################");
foreach (string netlistContainerName in NetlistContainerNames)
{
string anchor;
List <XDLContainer> nlcs = new List <XDLContainer>();
nlcs.Add((XDLContainer)NetlistContainerManager.Instance.Get(netlistContainerName));
bool anchorFound = XDLContainer.GetAnchor(nlcs, out anchor);
buffer.AppendLine("INST \"*inst_" + netlistContainerName + "\" LOC = \"" + anchor + "\"; # generated_by_GoAhead");
}
// write to file
if (File.Exists(FileName))
{
TextWriter tw = new StreamWriter(FileName);
tw.Write(buffer.ToString());
tw.Close();
}
// write to gui
OutputManager.WriteUCFOutput(buffer.ToString());
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
if (TileSelectionManager.Instance.NumberOfSelectedTiles == 0)
{
OutputManager.WriteOutput("Warning: No tiles selected");
}
// read file
DesignParser parser = DesignParser.CreateDesignParser(XDLInFile);
// into design
NetlistContainer inContainer = new XDLContainer();
parser.ParseDesign(inContainer, this);
// store selected parts in outDesign
XDLContainer outContainer = (XDLContainer)inContainer.GetSelectedDesignElements();
// write design to file
StreamWriter sw = new StreamWriter(XDLOutFile, false);
outContainer.WriteCodeToFile(sw);
sw.Close();
if (!string.IsNullOrEmpty(BinaryNetlist))
{
SaveXDLLibraryElementAsBinaryLibraryElement saveCmd = new SaveXDLLibraryElementAsBinaryLibraryElement();
saveCmd.FileName = BinaryNetlist;
saveCmd.XDLFileName = XDLOutFile;
CommandExecuter.Instance.Execute(saveCmd);
}
}
public static DesignParser CreateDesignParser(string fileName)
{
if (FPGA.FPGA.Instance.Family.Equals(FPGATypes.FPGAFamily.Undefined))
{
throw new ArgumentException("Can not load design " + fileName + " as no FPGA is loaded. Use OpenBinFPGA to open a device description first.");
}
if (!File.Exists(fileName))
{
throw new ArgumentException("File " + fileName + " not found");
}
switch (Path.GetExtension(fileName).ToLower())
{
case ".viv_nl":
FPGATypes.AssertBackendType(FPGATypes.BackendType.Vivado);
return(new TCLDesignParser(fileName));
case ".xdl":
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
return(new XDLDesignParser(fileName));
default:
throw new ArgumentException("The extension of the argument FileName must be either xdl or viv_nl (case insensitive), but found " + Path.GetExtension(fileName));
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
LibElemInst inst = LibraryElementInstanceManager.Instance.GetInstantiation(InstanceName);
LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName);
Tile anchorCLB = FPGA.FPGA.Instance.GetTile(inst.AnchorLocation);
NetlistContainer netlistContainer = GetNetlistContainer();
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
RelocateInstancesForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
RelocateNetsForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer);
// add design config
if (AddDesignConfig && libElement.Containter is XDLContainer && ((XDLContainer)netlistContainer).GetDesignConfig().Length == 0)
{
((XDLContainer)netlistContainer).AddDesignConfig(((XDLContainer)libElement.Containter).GetDesignConfig());
}
break;
case FPGATypes.BackendType.Vivado:
RelocateInstancesForTCL(libElement, anchorCLB, (TCLContainer)netlistContainer);
RelocateNetsForTCL(libElement, anchorCLB, netlistContainer);
break;
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
// extract net names as we may not remve during iteration
List <XDLNet> netNamesToDecompose = new List <XDLNet>();
foreach (string netName in NetNames)
{
XDLNet n = (XDLNet)netlistContainer.GetNet(netName);
netNamesToDecompose.Add(n);
}
foreach (XDLNet net in netNamesToDecompose)
{
foreach (XDLPip pip in net.Pips)
{
XDLNet arc = new XDLNet(net.Name + "_" + pip.Location + "_" + pip.From + "_" + pip.To);
// TODO what about attributes
arc.Add(pip);
netlistContainer.Add(arc);
}
net.ClearPips();
if (net.NetPinCount == 0)
{
netlistContainer.Remove(new Predicate <Net>(n => n.Name.Equals(net.Name)));
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
IEnumerable <string> clockRegions = FPGA.FPGA.Instance.GetAllTiles().Select(t => t.ClockRegion).Where(s => !string.IsNullOrEmpty(s)).Distinct().OrderBy(s => s);
OutputManager.WriteOutput("# clock region wise resource report for " + FPGA.FPGA.Instance.DeviceName);
OutputManager.WriteOutput("# the following clock regions will be reported " + string.Join(",", clockRegions));
OutputManager.WriteOutput("# ");
List <SetColumnTypeNames> addCommandsForUnknownTypes = new List <SetColumnTypeNames>();
foreach (string clockRegion in clockRegions)
{
// get upper row
int minX = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.X).Min();
int maxX = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.X).Max();
int minY = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.Y).Min();
int maxY = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.Y).Max();
int tileCount = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Count();
OutputManager.WriteOutput("########################################################################################## ");
OutputManager.WriteOutput("# report section for clock region " + clockRegion + " with " + tileCount + " tiles");
OutputManager.WriteOutput("# tiles contained in this clock region: " + string.Join(",", FPGA.FPGA.Instance.GetAllTiles().Select(t => t.Location)));
for (int x = minX; x <= maxX; x++)
{
string resources = "";
for (int y = minY; y <= maxY; y++)
{
Tile t = FPGA.FPGA.Instance.GetTile(x, y);
foreach (Slice s in t.Slices)
{
resources += s.SliceType + ",";
}
}
if (resources.EndsWith(","))
{
resources = resources.Remove(resources.Length - 1, 1);
}
SetColumnTypeNames addCmd = null;
string typeName = Objects.ColumnTypeNameManager.Instance.GetColumnTypeNameByResource(resources, out addCmd);
if (addCmd != null)
{
addCommandsForUnknownTypes.Add(addCmd);
}
OutputManager.WriteOutput("column=" + x + ",clock_region=" + clockRegion + ",type=" + typeName + ",resources=" + resources);
}
}
OutputManager.WriteOutput("########################################################################################## ");
OutputManager.WriteOutput("# for the columns with resource type unknown ");
OutputManager.WriteOutput("# you might use the following commands in init.goa ");
OutputManager.WriteOutput("# to provide a meaningful type name for that resource");
foreach (SetColumnTypeNames cmd in addCommandsForUnknownTypes)
{
OutputManager.WriteOutput("use " + cmd.ToString());
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
XDLContainer nlc = (XDLContainer)GetNetlistContainer();
AddTemplate(nlc, Template, Location, PrimitiveIndex);
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
foreach (XDLNet n in netlistContainer.Nets)
{
foreach (XDLPip pip in n.Pips)
{
Tile t = FPGA.FPGA.Instance.GetTile(pip.Location);
if (!IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))
{
continue;
}
foreach (Slice s in t.Slices)
{
bool inport = s.PortMapping.IsSliceInPort(new Port(pip.To));
bool outport = s.PortMapping.IsSliceOutPort(new Port(pip.To));
if ((inport | outport) && pip.To.Contains('_'))
{
NetPin pin = null;
if (inport)
{
pin = new NetInpin();
}
else
{
pin = new NetOutpin();
}
string[] atoms = pip.To.Split('_');
pin.SlicePort = atoms[1];
if (netlistContainer.Instances.Any(i => i.SliceName.Equals(s.SliceName)))
{
// there should be only one instance on the slice
XDLInstance inst = (XDLInstance)netlistContainer.Instances.First(i => i.SliceName.Equals(s.SliceName));
pin.InstanceName = inst.Name;
}
else
{
pin.InstanceName = s.SliceName;
}
bool pinExistsAlready = n.NetPins.FirstOrDefault(np => np.InstanceName.Equals(pin.InstanceName) && np.SlicePort.Equals(pin.SlicePort)) != null;
if (!pinExistsAlready)
{
n.Add(pin);
}
}
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer netlistContainer = GetNetlistContainer();
XDLNet net = (XDLNet )netlistContainer.GetNet(Netname);
Regex filter = new Regex(PipRegexp, RegexOptions.Compiled);
net.Remove(pip => filter.IsMatch(pip.ToString()));
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
Slice where = FPGA.FPGA.Instance.Current.Slices[SliceNumber];
XDLMacroPort addedPort = new XDLMacroPort(PortName, new Port(PortString), where);
XDLContainer netlistContainer = (XDLContainer)GetNetlistContainer();
netlistContainer.Add(addedPort);
}
public XDLFile(bool exportPortDeclarations, bool exportDummyNets, List <XDLContainer> netlistContainerNames, bool includeDesignStatement, bool includeModuleHeader, bool includeModuleFooter, string designName, bool sortInstancesBySliceName)
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
m_exportPortDeclarations = exportPortDeclarations;
m_exportDummyNets = exportDummyNets;
m_netlistContainer = netlistContainerNames;
m_includeDesignStatement = includeDesignStatement;
m_includeModuleHeader = includeModuleHeader;
m_includeModuleFooter = includeModuleFooter;
m_designName = designName;
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// read file
DesignParser parser = DesignParser.CreateDesignParser(FileName);
XDLContainer container = new XDLContainer();
// into design
parser.ParseDesign(container, this);
// derive name from file
string elementName = Path.GetFileNameWithoutExtension(FileName);
if (container.ModuleCount != 0)
{
// find ports to block and assign them to slices
// as we want to either
// connect these ports (if used) or
// drive a '1' to (if unused)
foreach (XDLModule module in container.Modules)
{
// new library element to be added to library
LibraryElement libElement = new LibraryElement();
libElement.Containter = module;
libElement.Name = elementName;
libElement.PrimitiveName = elementName;
libElement.LoadCommand = ToString();
// add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library
Objects.Library.Instance.Add(libElement);
DeriveBlockingData(libElement);
}
}
else
{
// new library element to be added to library
LibraryElement libElement = new LibraryElement();
libElement.Containter = container;
libElement.Name = elementName;
libElement.PrimitiveName = elementName;
libElement.LoadCommand = ToString();
// add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library
Objects.Library.Instance.Add(libElement);
DeriveBlockingData(libElement);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
CutOffISE();
break;
case FPGATypes.BackendType.Vivado:
CutOffVivado();
break;
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
PrintAreaGroupForISE();
break;
case FPGATypes.BackendType.Vivado:
PrintAreaGroupForVivado();
break;
default:
break;
}
}
protected override void DoCommandAction()
{
// Vivado only
FPGATypes.AssertBackendType(FPGATypes.BackendType.Vivado);
TCLContainer nlc = (TCLContainer)GetNetlistContainer();
bool closeStream = false;
if (m_sw == null)
{
// do not close external stream
closeStream = true;
m_sw = new StreamWriter(FileName, false);
}
WriteHeader(nlc, m_sw);
if (IncludeLinkDesignCommand)
{
//this.m_sw.WriteLine("link_design -name empty_netlist -part " + FPGA.FPGA.Instance.DeviceName);
}
// eingelesen aus Netzliste (also von Vivado erstellt!) genrieren (brauchen wir erstmal nicht, nur fuer eigene instanzen ggf neu Hierstufen ienziehen, siehe create_cell)
//this.WriteHierarchyCells(nlc);
WriteInstances(nlc);
//this.WritePins(nlc);
////this.WritePorts(nlc);
WriteNets(nlc);
m_sw.WriteLine("");
m_sw.WriteLine("# end of file");
if (closeStream)
{
m_sw.Close();
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
XDLContainer netlistContainer = (XDLContainer)GetNetlistContainer();
Port from = new Port(From);
Port to = new Port(To);
if (!FPGA.FPGA.Instance.Current.SwitchMatrix.Contains(from, to))
{
throw new ArgumentException("Tile " + FPGA.FPGA.Instance.Current + " does not contain arc " + from + " -> " + to);
}
if (FPGA.FPGA.Instance.Current.IsPortBlocked(from) && !((XDLNet)netlistContainer.LastNetAdded).Contains(FPGA.FPGA.Instance.Current, from))
{
throw new ArgumentException("Port " + from + " on slice " + FPGA.FPGA.Instance.Current + " is blocked by another net");
}
if (FPGA.FPGA.Instance.Current.IsPortBlocked(to) && !((XDLNet)netlistContainer.LastNetAdded).Contains(FPGA.FPGA.Instance.Current, to))
{
throw new ArgumentException("Port " + to + " on slice " + FPGA.FPGA.Instance.Current + " is blocked by another net");
}
if (netlistContainer == null)
{
throw new ArgumentException("No current macro");
}
if (netlistContainer.LastNetAdded == null)
{
throw new ArgumentException("No current net");
}
((XDLNet)netlistContainer.LastNetAdded).Add(FPGA.FPGA.Instance.Current, from, to);
if (!FPGA.FPGA.Instance.Current.IsPortBlocked(from))
{
FPGA.FPGA.Instance.Current.BlockPort(from, Tile.BlockReason.Blocked);
}
if (!FPGA.FPGA.Instance.Current.IsPortBlocked(to))
{
FPGA.FPGA.Instance.Current.BlockPort(to, Tile.BlockReason.Blocked);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.Vivado);
Mode mode = Mode.Undefined;
if (NetlistType.ToLower().Equals("static"))
{
mode = Mode.Static;
}
else if (NetlistType.ToLower().Equals("module"))
{
mode = Mode.Module;
}
else
{
throw new ArgumentException("Invalid value for NetlistType " + NetlistType + ". Use either static or module");
}
CheckRoutingResourceUsageInTunnel(mode);
CheckEnterLeave();
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
XDLContainer design = (XDLContainer)GetNetlistContainer();
XDLContainer blocker = new XDLContainer();
// read file
DesignParser parser = DesignParser.CreateDesignParser(Blocker);
// into design
parser.ParseDesign(blocker, this);
/*
* only the blocker net is deleted, the blocker instance remains part of the static design
* foreach (XDLInstance inst in blocker.Instances)
* {
* if (design.HasInstanceBySliceName(inst.SliceName))
* {
* this.OutputManager.WriteOutput("Resource conflict on instance " + inst.Name);
* }
* }*/
foreach (XDLNet net in blocker.Nets)
{
foreach (XDLPip pip in net.Pips)
{
Tile t = FPGA.FPGA.Instance.GetTile(pip.Location);
if (t.IsPortBlocked(pip.From))
{
OutputManager.WriteOutput("In net " + net.Name + ": resource conflict on FROM port " + pip);
}
if (t.IsPortBlocked(pip.To))
{
OutputManager.WriteOutput("In net " + net.Name + ": resource conflict on TO port " + pip);
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer nlc = GetNetlistContainer();
// look for net with outping
XDLNet anyNet = (XDLNet)nlc.Nets.FirstOrDefault(n => n.OutpinCount == 1 && string.IsNullOrEmpty(((XDLNet)n).HeaderExtension));
if (anyNet == null)
{
throw new ArgumentException("Could not a net with an outpin in " + NetlistContainerName);
}
// add outpin and inpin statements
foreach (XDLNet net in nlc.Nets.Where(net => OtherArcsFilter(anyNet, net)))
{
anyNet.Add(net, false);
// ports remain blocked
net.ClearPips();
net.ClearPins();
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer nlc = GetNetlistContainer();
foreach (XDLNet bufgNet in nlc.Nets.Where(n => ((XDLNet)n).NetPins.Count(np => np is NetOutpin && np.InstanceName.Contains(BUFGInstanceName)) > 0))
{
OutputManager.WriteOutput("Merging blocker into net " + bufgNet.Name);
foreach (string blockerFileName in XDLBlockerFiles)
{
NetlistContainer blocker = ReadBlocker(blockerFileName);
foreach (XDLNet blockerNet in blocker.Nets)
{
foreach (NetPin inpin in blockerNet.NetPins.Where(np => np is NetInpin && np.SlicePort.Contains("CLK")))
{
// add inpin to BUFG net
bufgNet.Add(inpin);
}
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
NetlistContainer netlistContainer = GetNetlistContainer();
bool arcAdded = false;
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
arcAdded = AddArcsXDL(netlistContainer);
break;
case FPGATypes.BackendType.Vivado:
arcAdded = AddArcsVivado((TCLContainer)netlistContainer);
break;
}
if (!arcAdded)
{
throw new ArgumentException("Did not find any tile in the current selection that contains the arcs " + From + " -> " + To + ". Misspelled From or To?");
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
DesignParser parser = DesignParser.CreateDesignParser(XDLFile);
XDLContainer container = new XDLContainer();
parser.ParseDesign(container, this);
VHDLParser moduleParser = new VHDLParser(VHDLModule);
VHDLParserEntity ent = moduleParser.GetEntity(0);
Dictionary <int, List <Signal> > east = new Dictionary <int, List <Signal> >();
Dictionary <int, List <Signal> > west = new Dictionary <int, List <Signal> >();
double xCenter, yCenter;
TileSelectionManager.Instance.GetCenterOfSelection(t => TileSelectionManager.Instance.IsSelected(t.TileKey), out xCenter, out yCenter);
foreach (HDLEntitySignal signal in ent.InterfaceSignals)
{
foreach (XDLNet net in container.Nets.Where(n => n.Name.StartsWith(signal.SignalName) && ((XDLNet)n).HasIndex()).OrderBy(n => ((XDLNet)n).GetIndex()))
{
Tile fromTile;
Tile toTile;
GetSourceAndSink(container, net, out fromTile, out toTile);
GetSourceAndSink(container, net, out fromTile, out toTile);
Tile innerTile = null;
Tile outerTile = null;
string signalMode = "";
if (!TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && TileSelectionManager.Instance.IsSelected(toTile.TileKey))
{
innerTile = toTile;
outerTile = fromTile;
signalMode = "in";
}
else if (TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && !TileSelectionManager.Instance.IsSelected(toTile.TileKey))
{
outerTile = toTile;
innerTile = fromTile;
signalMode = "out";
}
else
{
throw new ArgumentException("Expecting an instance inside the current selection");
}
FPGATypes.InterfaceDirection dir = outerTile.TileKey.X < (int)xCenter ? FPGATypes.InterfaceDirection.East : FPGATypes.InterfaceDirection.West;
Dictionary <int, List <Signal> > signalCollection = dir.Equals(FPGATypes.InterfaceDirection.East) ? east : west;
if (!signalCollection.ContainsKey(innerTile.TileKey.Y))
{
signalCollection.Add(innerTile.TileKey.Y, new List <Signal>());
}
Signal s = new Signal();
s.Column = -1;
s.SignalDirection = dir;
s.SignalMode = signalMode;
s.SignalName = net.Name;
signalCollection[innerTile.TileKey.Y].Add(s);
// weiter: vor verlaesst das gummiband die partielle flaeche?
// vektoren nach osten oder westen?
}
}
bool interleaveEast = east.Any(t => t.Value.Count > 4);
bool interleaveWest = west.Any(t => t.Value.Count > 4);
Dictionary <FPGA.FPGATypes.Direction, Dictionary <int, List <Signal> > > interfaces = new Dictionary <FPGATypes.Direction, Dictionary <int, List <Signal> > >();
interfaces.Add(FPGATypes.Direction.East, new Dictionary <int, List <Signal> >());
interfaces[FPGATypes.Direction.East][0] = new List <Signal>();
interfaces[FPGATypes.Direction.East][1] = new List <Signal>();
interfaces.Add(FPGATypes.Direction.West, new Dictionary <int, List <Signal> >());
interfaces[FPGATypes.Direction.West][0] = new List <Signal>();
interfaces[FPGATypes.Direction.West][1] = new List <Signal>();
if (interleaveEast)
{
int columnIndex = 0;
foreach (KeyValuePair <int, List <Signal> > tupel in east)
{
foreach (Signal s in tupel.Value)
{
Signal copy = new Signal(s.SignalName, s.SignalMode, s.SignalDirection, "", columnIndex);
interfaces[FPGATypes.Direction.East][columnIndex].Add(copy);
columnIndex++;
columnIndex %= 2;
}
}
}
//ent.InterfaceSignals
}
protected override void DoCommandAction()
{
if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado)
{
return;
}
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
NetlistContainer nlc = GetNetlistContainer();
int workload = GetNetsToDecomposeWithOutpin().Count();
int count = 0;
List <XDLNet> newNets = new List <XDLNet>();
foreach (XDLNet net in GetNetsToDecomposeWithOutpin().Where(n => n.PRLink))
{
ProgressInfo.Progress = ProgressStart + (int)((double)count++ / (double)workload * ProgressShare);
Dictionary <string, List <XDLPip> > pipsToRemove = null;
// decompose nets without outpin.
// e.g., placing a module on connection macros wil remove outpins from certain I/O bar wires
if (net.NetPins.Where(np => np is NetOutpin).Count() == 0)
{
pipsToRemove = new Dictionary <string, List <XDLPip> >();
foreach (XDLPip pip in net.Pips)
{
if (!pipsToRemove.ContainsKey(pip.Location))
{
pipsToRemove.Add(pip.Location, new List <XDLPip>());
}
pipsToRemove[pip.Location].Add(pip);
}
}
else
{
bool antenna = net.IsAntenna(out pipsToRemove);
}
bool firstArc = true;
// values are all non empty litst
foreach (List <XDLPip> l in pipsToRemove.Values)
{
foreach (XDLPip pip in l)
{
if (firstArc)
{
firstArc = false;
//this.OutputManager.WriteOutput("Decomposing net " + net.Name);
}
XDLNet arc = new XDLNet(net.Name + "_arc_" + pip.Location + "_" + pip.From + "_" + pip.To);
//arc.AddComment("decomposed from net (with outpin) " + net.Name);
// TODO what about attributes?
arc.Add(pip);
// move inpins
List <NetPin> netPinsToRemove = new List <NetPin>();
foreach (NetPin netpin in net.NetPins.Where(np => np is NetInpin))
{
XDLInstance inst = (XDLInstance)nlc.GetInstanceByName(netpin.InstanceName);
Tile pipTile = FPGA.FPGA.Instance.GetTile(pip.Location);
if (pipTile.TileKey.Equals(inst.TileKey))
{
//netpin.Comment += "taken from " + net.Name;
arc.Add(netpin);
// store net pip for later removal as we may not change the collection during iterating over it
netPinsToRemove.Add(netpin);
}
}
// remove the inpins from the original net ...
net.RemoveAllPinStatements(np => netPinsToRemove.Contains(np));
// ... and remove the arc from the original net
newNets.Add(arc);
}
}
// only invoke Remove once per net (blocker is very slow)
net.Remove(p => PipFilter(p, pipsToRemove));
}
// decompose blocker net
foreach (XDLNet net in GetNetsToDecomposeWithoutOutpin())
{
foreach (XDLPip pip in net.Pips)
{
XDLNet arc = new XDLNet(net.Name + "_arc_" + pip.Location + "_" + pip.From + "_" + pip.To);
//arc.AddComment("decomposed from net (without outpin) " + net.Name);
// TODO what about attributes?
arc.Add(pip);
newNets.Add(arc);
}
// remove all pips
net.ClearPips();
}
// add arcs
foreach (XDLNet n in newNets)
{
nlc.Add(n);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// what to route
NetlistContainer netlist = GetNetlistContainer();
XDLNet netToRoute = (XDLNet)netlist.GetNet(NetName);
int outpinCount = netToRoute.NetPins.Count(np => np is NetOutpin);
if (outpinCount != 1)
{
throw new ArgumentException("Can not route nets with " + outpinCount + " outpins");
}
NetPin outpin = netToRoute.NetPins.First(np => np is NetOutpin);
// start to route from here
List <Location> startLocations = new List <Location>();
List <Location> targetLocations = new List <Location>();
// route from outpin
string startTileName = netlist.GetInstanceByName(outpin.InstanceName).Location;
Tile startTile = FPGA.FPGA.Instance.GetTile(startTileName);
Slice startSlice = startTile.GetSliceByName(netlist.GetInstanceByName(outpin.InstanceName).SliceName);
Port startPip = startSlice.PortMapping.Ports.Where(p => p.Name.EndsWith(outpin.SlicePort)).First();
Location outpinLocation = new Location(startTile, startPip);
startLocations.Add(outpinLocation);
Queue <Location> targetQueue = new Queue <Location>(targetLocations);
foreach (NetPin inpin in netToRoute.NetPins.Where(np => np is NetInpin).OrderBy(np => np.InstanceName))
{
string targetTileName = netlist.GetInstanceByName(inpin.InstanceName).Location;
Tile targetTile = FPGA.FPGA.Instance.GetTile(targetTileName);
Slice targetSlice = targetTile.GetSliceByName(netlist.GetInstanceByName(inpin.InstanceName).SliceName);
Port targetPip = targetSlice.PortMapping.Ports.Where(p => p.Name.EndsWith(inpin.SlicePort)).First();
Location inpinLocation = new Location(targetTile, targetPip);
targetQueue.Enqueue(inpinLocation);
}
while (targetQueue.Count > 0)
{
// start with new routing
foreach (XDLPip pip in netToRoute.Pips)
{
Tile newStartTile = FPGA.FPGA.Instance.GetTile(pip.Location);
startLocations.Add(new Location(newStartTile, new Port(pip.From)));
}
// dequeue next target
Location targetLocation = targetQueue.Dequeue();
Watch.Start("route");
List <Location> revPath = Route(SearchMode, true, startLocations, targetLocation, 0, 100, false).FirstOrDefault();
Watch.Stop("route");
// extend net
if (revPath != null)
{
XDLNet extension = new XDLNet(revPath);
netToRoute.Add(extension);
}
}
// block the added pips
netToRoute.BlockUsedResources();
}
protected override void DoCommandAction()
{
BlockOnlyMarkedPortsScope = BlockOnlyMarkedPorts;
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
// prevent repeated error message from subcommands
if (!NetlistContainerManager.Instance.Contains(NetlistContainerName))
{
throw new ArgumentException("The netlist container " + NetlistContainerName + " does not exist. Use the command AddNetlistContainer to add a netlist container.");
}
NetlistContainer nlc = GetNetlistContainer();
Net blockerNet = null;
bool useExistingNet = false;
if (nlc.Nets.Any(n => n.OutpinCount > 0))
{
useExistingNet = true;
blockerNet = nlc.GetAnyNet();
OutputManager.WriteOutput("Adding blocker pips to already existing net " + blockerNet.Name);
}
else
{
// create XDL or TCL script
blockerNet = Net.CreateNet("BlockSelection");
if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado)
{
blockerNet = new TCLNet("BlockSelection");
//((TCLNet)blockerNet).Properties.SetProperty("IS_ROUTE_FIXED", "TRUE", false);
// tag for code generation
((TCLNet)blockerNet).IsBlockerNet = true;
((TCLNet)blockerNet).RoutingTree = new TCLRoutingTree();
TCLRoutingTreeNode root = new TCLRoutingTreeNode(null, null);
root.VirtualNode = true;
((TCLNet)blockerNet).RoutingTree.Root = root;
}
useExistingNet = false;
bool outPinAdded = false;
// the location string of the tile in which we run the outpin
string outpinLocation = "";
// 1 iterate over all not filtered out tiles to instantiate primitves and to find an outpin
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
AddXDLTemplates(nlc, blockerNet, ref outPinAdded, ref outpinLocation);
break;
case FPGATypes.BackendType.Vivado:
//this.AddTCLInstances(nlc, blockerNet, ref outPinAdded, ref outpinLocation);
((TCLContainer)nlc).AddGndPrimitive(blockerNet);
outPinAdded = true;
break;
}
// 2 name net according to added outpin
blockerNet.Name = Prefix + outpinLocation + "_" + blockerNet.Name;
if (!outPinAdded)
{
OutputManager.WriteOutput("Could not find an outpin");
}
}
// 4 cluster all completely unblocked tiles by their identifiers (do not cluster BEFORE having added and thus blocked an outpin)
// tiles with already blocked ports are added to single cluster each and thus treated seperately
Dictionary <int, List <Tile> > clusteredTiles = new Dictionary <int, List <Tile> >();
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
FindClusteringForISE(clusteredTiles);
break;
case FPGATypes.BackendType.Vivado:
FindClusteringForVivado(clusteredTiles);
break;
}
// block by
// 5 paths ...
int clusterCount = 0;
foreach (List <Tile> tiles in clusteredTiles.Values)
{
AddBlockerPaths(blockerNet, tiles[0], tiles);
ProgressInfo.Progress = 0 + (int)((double)clusterCount++ / (double)clusteredTiles.Count * 50);
}
// 6 and arcs
clusterCount = 0;
foreach (List <Tile> tiles in clusteredTiles.Values)
{
AddArcs(blockerNet, tiles[0], tiles);
ProgressInfo.Progress = 50 + (int)((double)clusterCount++ / (double)clusteredTiles.Count * 50);
}
// 7 check blocking
if (PrintUnblockedPorts)
{
foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles().Where(
t => !BlockerSettings.Instance.SkipTile(t) && IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect)))
{
CheckForUnblockedPorts(t);
}
}
// clean up indeces
foreach (Tile tile in TileSelectionManager.Instance.GetSelectedTiles().Where(t => !BlockerSettings.Instance.SkipTile(t)))
{
tile.SwitchMatrix.ClearBlockingPortList();
}
// add prefix and store nets
if (blockerNet.PipCount > 0 && !useExistingNet)
{
nlc.Add(blockerNet);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// read file
DesignParser parser = DesignParser.CreateDesignParser(XDLInFile);
// into design
XDLContainer container = new XDLContainer();
parser.ParseDesign(container, this);
XDLNet netWithOutPin = (XDLNet)container.Nets.FirstOrDefault(n => n.OutpinCount == 1 && string.IsNullOrEmpty(((XDLNet)n).HeaderExtension));
if (netWithOutPin == null)
{
throw new ArgumentException("No net with outpin found");
}
List <string> namesOfNetsWithoutOutpin = new List <string>();
foreach (Net net in container.Nets.Where(n => n.OutpinCount == 0))
{
namesOfNetsWithoutOutpin.Add(net.Name);
}
foreach (string netName in namesOfNetsWithoutOutpin)
{
XDLNet net = (XDLNet)container.Nets.FirstOrDefault(n => n.Name.Equals(netName));
if (net == null)
{
throw new ArgumentException("Net " + netName + " not found");
}
foreach (XDLPip pip in net.Pips)
{
netWithOutPin.Add(pip);
}
net.ClearPips();
}
System.IO.TextWriter tw = new System.IO.StreamWriter(XDLOutFile, false);
tw.WriteLine(container.GetDesignConfig().ToString());
foreach (XDLModule mod in container.Modules)
{
tw.WriteLine(mod.ToString());
}
foreach (XDLPort p in container.Ports)
{
tw.WriteLine(p.ToString());
}
foreach (XDLInstance inst in container.Instances)
{
tw.WriteLine(inst.ToString());
}
foreach (XDLNet net in container.Nets)
{
tw.WriteLine(net.ToString());
}
tw.Close();
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
int netsDone = 0;
int netCount = GetAllNets().Count();
foreach (XDLNet net in GetAllNets().Where(n => n.OutpinCount == 0))
{
Print("Found net without outpin: " + net.Name);
}
foreach (XDLNet net in GetAllNets())
{
ProgressInfo.Progress = ProgressStart + (int)((double)netsDone++ / (double)netCount * ProgressShare);
foreach (XDLPip pip in net.Pips)
{
Tile t = FPGA.FPGA.Instance.GetTile(pip.Location);
if (t.IsSliceOutPort(pip.From) || t.IsSliceInPort(pip.To) || pip.Operator.Equals("=-"))
{
continue;
}
List <Location> reachable = new List <Location>();
foreach (Location loc in Navigator.GetDestinations(pip.Location, pip.To))
{
reachable.Add(loc);
}
bool antennaHead = true;
foreach (Location loc in reachable)
{
// other pip
if (net.HasPip(p => p.Location.Equals(loc.Tile.Location) && p.From.Equals(loc.Pip.Name)))
{
antennaHead = false;
break;
}
// other long line, e.g. LH0 =- LV16,
if (net.HasPip(p => p.Location.Equals(loc.Tile.Location) && p.To.Equals(loc.Pip.Name) && p.Operator.Equals("=-")))
{
antennaHead = false;
break;
}
}
// stop over
if (net.HasPip(p => p.Location.Equals(pip.Location) && p.From.Equals(pip.To)))
{
antennaHead = false;
break;
}
if (antennaHead)
{
Print("-------- Antenna heads --------");
if (reachable.Count > 0)
{
Print("Net " + net.Name + " has island via " + pip + " as " + pip.To + " is connected to:");
foreach (Location l in reachable)
{
Print("--> " + l.ToString() + " which is not continued within the net");
}
}
else
{
Print("Net " + net.Name + " has island via " + pip + " which is not continued within the net");
}
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
SortMode mode = SortMode.Undefined;
HMode hMode = HMode.Undefined;
VMode vMode = VMode.Undefined;
SetSortModes(ref mode, ref hMode, ref vMode);
List <TileKey> keys = new List <TileKey>();
foreach (Tile tile in TileSelectionManager.Instance.GetSelectedTiles().Where(t =>
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.Interconnect)))
{
keys.Add(tile.TileKey);
}
var preOrderedKey =
from key in keys
group key by(mode == SortMode.R?key.Y : key.X) into g
select g;
List <Tile> tilesInFinalOrder = new List <Tile>();
if (mode == SortMode.R)
{
foreach (IGrouping <int, TileKey> group in (vMode == VMode.TD ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (hMode == HMode.L2R ? group.OrderBy(k => k.X) : group.OrderBy(k => k.X).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
else
{
foreach (IGrouping <int, TileKey> group in (hMode == HMode.L2R ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (vMode == VMode.TD ? group.OrderBy(k => k.Y) : group.OrderBy(k => k.Y).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
int index = StartIndex;
foreach (Tile tile in tilesInFinalOrder)
{
foreach (string path in Paths)
{
string netName = Prefix + SignalName + "[" + index++ + "]";
PRLink link = new PRLink(tile, netName);
string[] portNames = path.Split(':');
foreach (string portName in portNames)
{
if (!tile.SwitchMatrix.Contains(portName))
{
throw new ArgumentException("Port " + portName + " not found on " + tile.Location);
}
link.Add(new Port(portName));
tile.BlockPort(portName, Tile.BlockReason.ExcludedFromBlocking);
}
PRLinkManager.Instance.Add(link);
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
XDLContainer nlc = (XDLContainer)GetNetlistContainer();
List <string> fixedSliceConfigurations = new List <string>();
foreach (XDLInstance inst in nlc.Instances)
{
// A5LUT:Inst_PE/Mmult_OPA[31]_OPB[31]_MuLt_17_OUT_Madd10_cy<6>:#LUT -> A5LUT::#LUT
string originalCode = inst.ToString();
string fixedCode = originalCode;
if (!fixedCode.Contains("A5LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " A5LUT:(.+?):#LUT:", " A5LUT::#LUT:");
}
if (!fixedCode.Contains("B5LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " B5LUT:(.+?):#LUT:", " B5LUT::#LUT:");
}
if (!fixedCode.Contains("C5LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " C5LUT:(.+?):#LUT:", " C5LUT::#LUT:");
}
if (!fixedCode.Contains("D5LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " D5LUT:(.+?):#LUT:", " D5LUT::#LUT:");
}
if (!fixedCode.Contains("A6LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " A6LUT:(.+?):#LUT:", " A6LUT::#LUT:");
}
if (!fixedCode.Contains("B6LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " B6LUT:(.+?):#LUT:", " B6LUT::#LUT:");
}
if (!fixedCode.Contains("C6LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " C6LUT:(.+?):#LUT:", " C6LUT::#LUT:");
}
if (!fixedCode.Contains("D6LUT::#OFF"))
{
fixedCode = Regex.Replace(fixedCode, " D6LUT:(.+?):#LUT:", " D6LUT::#LUT:");
}
// neu
// A5FF:Inst_PE/Mmult_OPA[31]_OPB[31]_MuLt_18_OUT_OPA,OPB<20>_x_OPA,OPB<62>_mand1_FRB: -> A5FF::
if (!fixedCode.Contains("A5FF::"))
{
fixedCode = Regex.Replace(fixedCode, "A5FF:(.+?):", "A5FF::");
}
if (!fixedCode.Contains("B5FF::"))
{
fixedCode = Regex.Replace(fixedCode, "B5FF:(.+?):", "B5FF::");
}
if (!fixedCode.Contains("C5FF::"))
{
fixedCode = Regex.Replace(fixedCode, "C5FF:(.+?):", "C5FF::");
}
if (!fixedCode.Contains("D5FF::"))
{
fixedCode = Regex.Replace(fixedCode, "D5FF:(.+?):", "D5FF::");
}
// BFF:Inst_PE/config_data_en_0:#FF --> BFF::#FF
if (!fixedCode.Contains("AFF::#OFF") && !fixedCode.Contains("AFF::#FF"))
{
fixedCode = Regex.Replace(fixedCode, "AFF:(.+?):", "AFF::");
}
if (!fixedCode.Contains("BFF::#OFF") && !fixedCode.Contains("BFF::#FF"))
{
fixedCode = Regex.Replace(fixedCode, "BFF:(.+?):", "BFF::");
}
if (!fixedCode.Contains("CFF::#OFF") && !fixedCode.Contains("CFF::#FF"))
{
fixedCode = Regex.Replace(fixedCode, "CFF:(.+?):", "CFF::");
}
if (!fixedCode.Contains("DFF::#OFF") && !fixedCode.Contains("DFF::#FF"))
{
fixedCode = Regex.Replace(fixedCode, "DFF:(.+?):", "DFF::");
}
fixedSliceConfigurations.Add(fixedCode);
}
nlc.Remove(delegate(Instance i) { return(true); });
foreach (string xdlCode in fixedSliceConfigurations)
{
nlc.AddSliceCodeBlock(xdlCode);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado);
SortMode mode = SortMode.Undefined;
HMode hMode = HMode.Undefined;
VMode vMode = VMode.Undefined;
SetSortModes(ref mode, ref hMode, ref vMode);
List <TileKey> keys = new List <TileKey>();
foreach (Tile clb in TileSelectionManager.Instance.GetSelectedTiles().Where(t =>
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB) ||
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.DSP) ||
IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.BRAM)))
{
keys.Add(clb.TileKey);
}
var preOrderedKey =
from key in keys
group key by(mode == SortMode.R?key.Y : key.X) into g
select g;
List <Tile> tilesInFinalOrder = new List <Tile>();
if (mode == SortMode.R)
{
foreach (IGrouping <int, TileKey> group in (vMode == VMode.TD ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (hMode == HMode.L2R ? group.OrderBy(k => k.X) : group.OrderBy(k => k.X).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
else
{
foreach (IGrouping <int, TileKey> group in (hMode == HMode.L2R ? preOrderedKey.OrderBy(g => g.Key) : preOrderedKey.OrderByDescending(g => g.Key)))
{
foreach (TileKey key in (vMode == VMode.TD ? group.OrderBy(k => k.Y) : group.OrderBy(k => k.Y).Reverse()))
{
tilesInFinalOrder.Add(FPGA.FPGA.Instance.GetTile(key));
}
}
}
// apply filter
tilesInFinalOrder.RemoveAll(t => !Regex.IsMatch(t.Location, Filter));
/*
* // check prior to plaecment of valid placement
* foreach (Tile t in tilesInFinalOrder)
* {
* LibraryElement libElement = Objects.Library.Instance.GetElement(this.LibraryElementName);
* StringBuilder errorList = null;
* bool placementOk = DesignRuleChecker.CheckLibraryElementPlacement(t, libElement, out errorList);
* if (!placementOk)
* {
* throw new ArgumentException("Macro " + this.LibraryElementName + " can not be placed at " + t + ": " + errorList.ToString());
* }
* }
*/
if (AutoClearModuleSlot)
{
LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName);
AutoClearModuleSlotBeforeInstantiation(libElement, tilesInFinalOrder);
}
foreach (Tile t in tilesInFinalOrder)
{
// check again prior to placement and now consider already placed tiles
/*
* StringBuilder errorList = null;
* bool placementOk = DesignRuleChecker.CheckLibraryElementPlacement(t, libElement, out errorList);
* if (!placementOk)
* {
* throw new ArgumentException("Library element " + this.LibraryElementName + " can not be placed at " + t + ": " + errorList.ToString());
* }*/
switch (FPGA.FPGA.Instance.BackendType)
{
case FPGATypes.BackendType.ISE:
AddISEInstantiation(t);
break;
case FPGATypes.BackendType.Vivado:
AddVivadoInstantiation(t);
break;
}
}
if (AutoFuse)
{
FuseNets fuseCmd = new FuseNets();
fuseCmd.NetlistContainerName = NetlistContainerName;
fuseCmd.Mute = Mute;
fuseCmd.Profile = Profile;
fuseCmd.PrintProgress = PrintProgress;
CommandExecuter.Instance.Execute(fuseCmd);
}
}
