/// <summary> /// Receives a series of decimal addresses, and simulates cache entries and access as well /// as hit/miss info. Uses 16-bit addresses and 32-bit instructions. /// </summary> /// <param name="args"></param> static void Main(string[] args) { int[] instruction_set = { 4, 8, 12, 16, 20, 32, 36, 40, 44, 20, 32, 36, 40, 44, 64, 68, 4, 8, 12, 92, 96, 100, 104, 108, 112, 100, 112, 116, 120, 128, 140, 144 }; // Instantiate each cache type FullyAssoc fa = new FullyAssoc(4, 6); int FA_bit = FA_Bits(4); DirectMapped dm = new DirectMapped(4, 6); int DM_bit = DM_Bits(4); SetAssoc sa = new SetAssoc(2, 2, 6); int SA_bit = SA_Bits(2, 2); // Cycle trackers int FA_Cycles = 0; int DM_Cycles = 0; int SA_Cycles = 0; // H/M Trackers int FA_tally = 0; int DM_tally = 0; int SA_tally = 0; // H/M Arrays string[] FA_Hit = new string[32]; string[] DM_Hit = new string[32]; string[] SA_Hit = new string[32]; // Test each instruction twice on each cache! for (int iteration = 1; iteration <= 2; iteration++) { for (int i = 0; i < 32; i++) { // FA if (fa.Access(instruction_set[i]) && iteration == 2) { FA_Hit[i] = "H"; FA_tally += 1; FA_Cycles += 1; } else { FA_Hit[i] = "M"; FA_Cycles += 17; } //DM if (dm.Access(instruction_set[i]) && iteration == 2) { DM_Cycles += 1; DM_Hit[i] = "H"; DM_tally += 1; } else { DM_Cycles += 17; DM_Hit[i] = "M"; } //SA if (sa.Access(instruction_set[i]) && iteration == 2) { SA_Cycles += 1; SA_Hit[i] = "H"; SA_tally += 1; } else { SA_Cycles += 17; SA_Hit[i] = "M"; } } } // Display FA Console.WriteLine("Fully-Associative Cache: 6 Byte Blocks, 4 Rows"); Console.WriteLine("Cache size: " + FA_bit); Console.WriteLine("Cache miss time: 1 cycle + 10 cycle penalty + 6 Byte Blocks per cycle = 17 cycles"); Console.WriteLine(FA_tally + " hits, " + (32 - FA_tally) + " misses."); Console.WriteLine("Avg CPI = " + FA_Cycles); Console.WriteLine("Valid|Tag|LRU"); fa.PrintData(); Console.WriteLine(); // Display DM Console.WriteLine("Direct-Mapped Cache: 6 Byte Blocks, 4 Rows"); Console.WriteLine("Cache size: " + DM_bit); Console.WriteLine("Cache miss time: 1 cycle + 10 cycle penalty + 6 Byte Blocks per cycle = 17 cycles"); Console.WriteLine(DM_tally + " hits, " + (32 - DM_tally) + " misses."); Console.WriteLine("Avg CPI = " + DM_Cycles); Console.WriteLine("Valid|Tag"); dm.PrintData(); Console.WriteLine(); // Display SA Console.WriteLine("Fully-Associative Cache: 6 Byte Blocks, 4 Rows"); Console.WriteLine("Cache size: " + SA_bit); Console.WriteLine("Cache miss time: 1 cycle + 10 cycle penalty + 6 Byte Blocks per cycle = 17 cycles"); Console.WriteLine(SA_tally + " hits, " + (32 - SA_tally) + " misses."); Console.WriteLine("Avg CPI = " + SA_Cycles); Console.WriteLine("Valid|Tag|LRU"); sa.PrintData(); Console.WriteLine(); Console.Read(); }
public void DM_Simple() { // 2-entry cache, that has 2 blocks of memory DirectMapped dm = new DirectMapped(2, 2); int sum = 0; if (dm.Access(24)) { sum += 1; //M add A } if (dm.Access(28)) { sum += 1; //H } if (dm.Access(92)) { sum += 1; //M add A } if (dm.Access(88)) { sum += 1; //H } if (dm.Access(24)) { sum += 1; //M add A } if (dm.Access(16)) { sum += 1; //M add B } if (dm.Access(28)) { sum += 1; //H } if (dm.Access(20)) { sum += 1; //H } Assert.AreEqual(4, sum); // All Misses: Skip every other block (1 block = 8) dm = new DirectMapped(2, 2); sum = 0; for (int i = 0; i < 1025; i += 8) { if (dm.Access(i)) { sum += 1; //M } } Assert.AreEqual(0, sum); // Get every block, hit every other time dm = new DirectMapped(2, 2); sum = 0; for (int i = 0; i < 1025; i += 4) { if (dm.Access(i)) { sum += 1; //M } } Assert.AreEqual(128, sum); }