protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
if (TileSelectionManager.Instance.NumberOfSelectedTiles == 0)
{
OutputManager.WriteOutput("Warning: No tiles selected");
}
// read file
DesignParser parser = DesignParser.CreateDesignParser(XDLInFile);
// into design
NetlistContainer inContainer = new XDLContainer();
parser.ParseDesign(inContainer, this);
// store selected parts in outDesign
XDLContainer outContainer = (XDLContainer)inContainer.GetSelectedDesignElements();
// write design to file
StreamWriter sw = new StreamWriter(XDLOutFile, false);
outContainer.WriteCodeToFile(sw);
sw.Close();
if (!string.IsNullOrEmpty(BinaryNetlist))
{
SaveXDLLibraryElementAsBinaryLibraryElement saveCmd = new SaveXDLLibraryElementAsBinaryLibraryElement();
saveCmd.FileName = BinaryNetlist;
saveCmd.XDLFileName = XDLOutFile;
CommandExecuter.Instance.Execute(saveCmd);
}
}
protected override void DoCommandAction()
{
int slicesMax = 0;
int dspMax = 0;
int bramMax = 0;
foreach (string fileName in Files.Where(s => !string.IsNullOrEmpty(s)))
{
int slices = 0;
int dsp = 0;
int bram = 0;
// read file
DesignParser parser = DesignParser.CreateDesignParser(fileName);
// into design
NetlistContainer inContainer = new NetlistContainer();
parser.ParseDesign(inContainer, this);
foreach (Instance inst in inContainer.Instances)
{
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.CLB))
{
slices++;
}
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.DSP))
{
dsp++;
}
if (IdentifierManager.Instance.IsMatch(inst.Location, IdentifierManager.RegexTypes.BRAM))
{
bram++;
}
}
if (slices > slicesMax)
{
slicesMax = slices;
}
if (dsp > dspMax)
{
dspMax = dsp;
}
if (bram > bramMax)
{
bramMax = bram;
}
// TODO chains erkennen
}
// two slices per CLB
OutputManager.WriteOutput("CLBs: " + slicesMax / 2 + " DSPs: " + dspMax + " BRAMs: " + bramMax);
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// read file
DesignParser parser = DesignParser.CreateDesignParser(FileName);
XDLContainer container = new XDLContainer();
// into design
parser.ParseDesign(container, this);
// derive name from file
string elementName = Path.GetFileNameWithoutExtension(FileName);
if (container.ModuleCount != 0)
{
// find ports to block and assign them to slices
// as we want to either
// connect these ports (if used) or
// drive a '1' to (if unused)
foreach (XDLModule module in container.Modules)
{
// new library element to be added to library
LibraryElement libElement = new LibraryElement();
libElement.Containter = module;
libElement.Name = elementName;
libElement.PrimitiveName = elementName;
libElement.LoadCommand = ToString();
// add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library
Objects.Library.Instance.Add(libElement);
DeriveBlockingData(libElement);
}
}
else
{
// new library element to be added to library
LibraryElement libElement = new LibraryElement();
libElement.Containter = container;
libElement.Name = elementName;
libElement.PrimitiveName = elementName;
libElement.LoadCommand = ToString();
// add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library
Objects.Library.Instance.Add(libElement);
DeriveBlockingData(libElement);
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
XDLContainer design = (XDLContainer)GetNetlistContainer();
XDLContainer blocker = new XDLContainer();
// read file
DesignParser parser = DesignParser.CreateDesignParser(Blocker);
// into design
parser.ParseDesign(blocker, this);
/*
* only the blocker net is deleted, the blocker instance remains part of the static design
* foreach (XDLInstance inst in blocker.Instances)
* {
* if (design.HasInstanceBySliceName(inst.SliceName))
* {
* this.OutputManager.WriteOutput("Resource conflict on instance " + inst.Name);
* }
* }*/
foreach (XDLNet net in blocker.Nets)
{
foreach (XDLPip pip in net.Pips)
{
Tile t = FPGA.FPGA.Instance.GetTile(pip.Location);
if (t.IsPortBlocked(pip.From))
{
OutputManager.WriteOutput("In net " + net.Name + ": resource conflict on FROM port " + pip);
}
if (t.IsPortBlocked(pip.To))
{
OutputManager.WriteOutput("In net " + net.Name + ": resource conflict on TO port " + pip);
}
}
}
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
DesignParser parser = DesignParser.CreateDesignParser(XDLFile);
XDLContainer container = new XDLContainer();
parser.ParseDesign(container, this);
VHDLParser moduleParser = new VHDLParser(VHDLModule);
VHDLParserEntity ent = moduleParser.GetEntity(0);
Dictionary <int, List <Signal> > east = new Dictionary <int, List <Signal> >();
Dictionary <int, List <Signal> > west = new Dictionary <int, List <Signal> >();
double xCenter, yCenter;
TileSelectionManager.Instance.GetCenterOfSelection(t => TileSelectionManager.Instance.IsSelected(t.TileKey), out xCenter, out yCenter);
foreach (HDLEntitySignal signal in ent.InterfaceSignals)
{
foreach (XDLNet net in container.Nets.Where(n => n.Name.StartsWith(signal.SignalName) && ((XDLNet)n).HasIndex()).OrderBy(n => ((XDLNet)n).GetIndex()))
{
Tile fromTile;
Tile toTile;
GetSourceAndSink(container, net, out fromTile, out toTile);
GetSourceAndSink(container, net, out fromTile, out toTile);
Tile innerTile = null;
Tile outerTile = null;
string signalMode = "";
if (!TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && TileSelectionManager.Instance.IsSelected(toTile.TileKey))
{
innerTile = toTile;
outerTile = fromTile;
signalMode = "in";
}
else if (TileSelectionManager.Instance.IsSelected(fromTile.TileKey) && !TileSelectionManager.Instance.IsSelected(toTile.TileKey))
{
outerTile = toTile;
innerTile = fromTile;
signalMode = "out";
}
else
{
throw new ArgumentException("Expecting an instance inside the current selection");
}
FPGATypes.InterfaceDirection dir = outerTile.TileKey.X < (int)xCenter ? FPGATypes.InterfaceDirection.East : FPGATypes.InterfaceDirection.West;
Dictionary <int, List <Signal> > signalCollection = dir.Equals(FPGATypes.InterfaceDirection.East) ? east : west;
if (!signalCollection.ContainsKey(innerTile.TileKey.Y))
{
signalCollection.Add(innerTile.TileKey.Y, new List <Signal>());
}
Signal s = new Signal();
s.Column = -1;
s.SignalDirection = dir;
s.SignalMode = signalMode;
s.SignalName = net.Name;
signalCollection[innerTile.TileKey.Y].Add(s);
// weiter: vor verlaesst das gummiband die partielle flaeche?
// vektoren nach osten oder westen?
}
}
bool interleaveEast = east.Any(t => t.Value.Count > 4);
bool interleaveWest = west.Any(t => t.Value.Count > 4);
Dictionary <FPGA.FPGATypes.Direction, Dictionary <int, List <Signal> > > interfaces = new Dictionary <FPGATypes.Direction, Dictionary <int, List <Signal> > >();
interfaces.Add(FPGATypes.Direction.East, new Dictionary <int, List <Signal> >());
interfaces[FPGATypes.Direction.East][0] = new List <Signal>();
interfaces[FPGATypes.Direction.East][1] = new List <Signal>();
interfaces.Add(FPGATypes.Direction.West, new Dictionary <int, List <Signal> >());
interfaces[FPGATypes.Direction.West][0] = new List <Signal>();
interfaces[FPGATypes.Direction.West][1] = new List <Signal>();
if (interleaveEast)
{
int columnIndex = 0;
foreach (KeyValuePair <int, List <Signal> > tupel in east)
{
foreach (Signal s in tupel.Value)
{
Signal copy = new Signal(s.SignalName, s.SignalMode, s.SignalDirection, "", columnIndex);
interfaces[FPGATypes.Direction.East][columnIndex].Add(copy);
columnIndex++;
columnIndex %= 2;
}
}
}
//ent.InterfaceSignals
}
protected override void DoCommandAction()
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
// read file
DesignParser parser = DesignParser.CreateDesignParser(XDLInFile);
// into design
XDLContainer container = new XDLContainer();
parser.ParseDesign(container, this);
XDLNet netWithOutPin = (XDLNet)container.Nets.FirstOrDefault(n => n.OutpinCount == 1 && string.IsNullOrEmpty(((XDLNet)n).HeaderExtension));
if (netWithOutPin == null)
{
throw new ArgumentException("No net with outpin found");
}
List <string> namesOfNetsWithoutOutpin = new List <string>();
foreach (Net net in container.Nets.Where(n => n.OutpinCount == 0))
{
namesOfNetsWithoutOutpin.Add(net.Name);
}
foreach (string netName in namesOfNetsWithoutOutpin)
{
XDLNet net = (XDLNet)container.Nets.FirstOrDefault(n => n.Name.Equals(netName));
if (net == null)
{
throw new ArgumentException("Net " + netName + " not found");
}
foreach (XDLPip pip in net.Pips)
{
netWithOutPin.Add(pip);
}
net.ClearPips();
}
System.IO.TextWriter tw = new System.IO.StreamWriter(XDLOutFile, false);
tw.WriteLine(container.GetDesignConfig().ToString());
foreach (XDLModule mod in container.Modules)
{
tw.WriteLine(mod.ToString());
}
foreach (XDLPort p in container.Ports)
{
tw.WriteLine(p.ToString());
}
foreach (XDLInstance inst in container.Instances)
{
tw.WriteLine(inst.ToString());
}
foreach (XDLNet net in container.Nets)
{
tw.WriteLine(net.ToString());
}
tw.Close();
}
protected override void DoCommandAction()
{
NetlistContainer nlc = GetNetlistContainer();
DesignParser parser = DesignParser.CreateDesignParser(FileName);
try
{
parser.ParseDesign(nlc, this);
}
catch (Exception e)
{
throw new ArgumentException("Error during parsing the design " + FileName + ": " + e.Message + ". Are you trying to open the design on the correct device?");
}
foreach (Instance inst in nlc.Instances)
{
Tile t = FPGA.FPGA.Instance.GetTile(inst.Location);
if (!t.HasSlice(inst.SliceName))
{
OutputManager.WriteWarning("Can not find primitve " + inst.SliceName + " on tile " + t.Location);
}
else
{
Slice s = t.GetSliceByName(inst.SliceName);
s.Usage = FPGATypes.SliceUsage.Macro;
if (FPGA.FPGA.Instance.BackendType == FPGATypes.BackendType.Vivado)
{
TCLInstance tclInst = (TCLInstance)inst;
if (!string.IsNullOrEmpty(tclInst.BELType))
{
s.SetBelUsage(tclInst.BELType, FPGATypes.SliceUsage.Macro);
}
}
}
}
foreach (Net n in nlc.Nets)
{
n.BlockUsedResources();
}
if (AutoFixXDLBugs)
{
FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE);
if (FPGA.FPGA.Instance.Family == FPGATypes.FPGAFamily.Spartan6)
{
foreach (XDLInstance inst in nlc.Instances.Where(i => i.Location.Contains("IOB") || i.SliceType.Equals("IOB")))
{
string code = inst.ToString();
if (!code.Contains("OUTBUF:"))
{
code = code.Replace("PRE_EMPHASIS::#OFF", "");
inst.SetCode(code);
OutputManager.WriteWarning("Fixed XDL code for instance " + inst.Name);
}
}
}
}
}
protected override void DoCommandAction()
{
TCLContainer nlc = new TCLContainer("VivadoLibraryElement");
DesignParser parser = DesignParser.CreateDesignParser(FileName);
try
{
parser.ParseDesign(nlc, this);
}
catch (Exception e)
{
throw new ArgumentException("Error during parsing the design " + FileName + ": " + e.Message + ". Are you trying to open the design on the correct device?");
}
LibraryElement libElement = new LibraryElement();
libElement.VivadoConnectionPrimitive = false;
libElement.PrimitiveName = Path.GetFileNameWithoutExtension(FileName);
libElement.Containter = nlc;
libElement.Name = Path.GetFileNameWithoutExtension(FileName);
libElement.LoadCommand = ToString();
libElement.ResourceShape = new Shape();
foreach (Instance inst in nlc.Instances)
{
libElement.ResourceShape.Add(inst.Location);
}
// X Y coordinates
int minX = nlc.Instances.Select(i => i.TileKey.X).Min();
int maxX = nlc.Instances.Select(i => i.TileKey.X).Max();
int minY = nlc.Instances.Select(i => i.TileKey.Y).Min();
int maxY = nlc.Instances.Select(i => i.TileKey.Y).Max();
// get covering rectangle
IEnumerable <Tile> rectangle =
from tile in FPGA.FPGA.Instance.GetAllTiles()
where
(IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB) ||
IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.BRAM) ||
IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.DSP)) &&
tile.TileKey.X >= minX && tile.TileKey.X <= maxX &&
tile.TileKey.Y >= minY && tile.TileKey.Y <= maxY
select tile;
// Row Column
int minRX = rectangle.Select(t => t.LocationX).Min();
int maxCY = rectangle.Select(t => t.LocationY).Max();
IEnumerable <Tile> possibleAnchors =
from tile in rectangle
where tile.LocationX == minRX && tile.LocationY == maxCY
select tile;
Tile anchor = possibleAnchors.OrderBy(t => t.TileKey.X).FirstOrDefault();
if (anchor == null)
{
throw new ArgumentException("No upper left tile of either type CLB, DSP or BRAM found. Can not derive any anchor.");
}
libElement.ResourceShape.Anchor.AnchorTileLocation = anchor.Location;
libElement.ResourceShape.Anchor.AnchorLocationX = anchor.LocationX;
libElement.ResourceShape.Anchor.AnchorLocationY = anchor.LocationY;
libElement.ResourceShape.Anchor.AnchorSliceNumber = 0;
libElement.ResourceShape.Anchor.AnchorSliceName = anchor.Slices[0].SliceName;
Objects.Library.Instance.Add(libElement);
}
