public RBLA_Monitor(MemCtrl mctrl, DDR3DRAM.Timing tc, DDR3DRAM.Timing old_tc) { _mctrl = mctrl; migration_cost = (int)tc.tLISA_INTER_SA_COPY; _act = 0; _actGain = (int)(old_tc.tRCD - tc.tRCD); _pre = 0; _preGain = (int)(old_tc.tRP - tc.tRP); _prevNetBenefit = 0; _prevAdjust = false; }
public RBLA_Stats(uint cacheSize, uint cacheAssoc, uint cacheBlockSize, uint hitLatency, uint cid, uint rid, uint bid, DDR3DRAM.Timing slow_tc) : base(cacheSize, cacheAssoc, cacheBlockSize, hitLatency, -1, false) { rb_BBC = new RblaCounter[SetMax, cacheAssoc]; for (int i = 0; i < SetMax; i++) { for (int j = 0; j < Assoc; j++) { rb_BBC[i, j].Benefit = 0; rb_BBC[i, j].ColumnStreak = 0; } } // Number of column commands needed to outweigh tRAS _trasColumnLen = (int)Math.Floor(((double)(slow_tc.tRAS - slow_tc.tCL)) / slow_tc.tCCD); RbCacheThreshold = Config.mctrl.rbla_cache_threshold; }