/// <summary> /// this is what causes the whole thing to run. /// </summary> public static void step() { // interrupt master flag enabled // and MMU interrupt enabled && MM interrupt flag if (Z80._r.ime && MMU._ie != 0 && MMU._if != 0) { // don't halt, disable master interrupt flag Z80._halt = false; Z80._r.ime = false; // if interrupt enable bit 1 set and interrupt flag 1 set if (((MMU._ie & 1) != 0) && ((MMU._if & 1) != 0)) { // clear interrupt flag 1, trigger reset to 0x40 MMU._if &= 0xFE; Z80._ops.RST40(); } } else { // halted - do nothing if (Z80._halt) { Z80._r.m = 1; } else { Z80._r.r = (Z80._r.r + 1) & 127; Z80._map[MMU.rb(Z80._r.pc++)](); // wrap PC to 16 bits //Z80._r.pc &= 0xFF; // handled in PC setter } } Z80._clock.m += Z80._r.m; Z80._clock.t += (Z80._r.m * 4); GPU.checkline(); if (Z80._stop) { pause(); } //dbgupdate(); }
public static void frame() { // a frame takes 17556 clock cycles to render. we're stuck here until it's complete. var fclock = Z80._clock.m + 17556; //var brk = document.getElementById('breakpoint').value; //var t0 = new Date(); do { // if halted, do nothing and increment m if (Z80._halt) { Z80._r.m = 1; } else { // Z80._r.r = (Z80._r.r+1) & 127; // increment and execute PC Z80._map[MMU.rb(Z80._r.pc++)](); // wrap PC to 16 bits - now handled in PC setter //Z80._r.pc &= 65535; } // if interrupt master enabled and any interrupts enabled and any interrupts triggered if (Z80._r.ime && MMU._ie != 0 && MMU._if != 0) { // disable interrupts Z80._halt = false; Z80._r.ime = false; // get fired interrupts that are enabled var ifired = MMU._ie & MMU._if; // interrupts get triggered according to priority (see page 40) if ((ifired & (1 << 0)) != 0) { MMU._if &= 0xFE; Z80._ops.RST40(); } // V-Blank else if ((ifired & (1 << 1)) != 0) { MMU._if &= 0xFD; Z80._ops.RST48(); } // LCDC (see STAT) else if ((ifired & (1 << 2)) != 0) { MMU._if &= 0xFB; Z80._ops.RST50(); } // Timer Overflow else if ((ifired & (1 << 3)) != 0) { MMU._if &= 0xF7; Z80._ops.RST58(); } // Serial I/O Complete else if ((ifired & (1 << 4)) != 0) { MMU._if &= 0xEF; Z80._ops.RST60(); } // P10-P13 transition H => L else { Z80._r.ime = true; } // otherwise, re-enable IME } //jsGB.dbgtrace(); Z80._clock.m += Z80._r.m; GPU.checkline(); TIMER.inc(); //if ((brk && parseInt(brk, 16) == Z80._r.pc) || Z80._stop) //{ // jsGB.pause(); // break; //} } while (Z80._clock.m < fclock); //var t1 = new Date(); //document.getElementById('fps').innerHTML = Math.round(10000 / (t1 - t0)) / 10; }
public static void wb(int addr, int val) { var gaddr = addr - 0xFF40; GPU._reg[gaddr] = val; switch (gaddr) { case 0: GPU._lcdon = (val & 0x80) != 0 ? 1 : 0; GPU._bgtilebase = (val & 0x10) != 0 ? 0x0000 : 0x0800; GPU._bgmapbase = (val & 0x08) != 0 ? 0x1C00 : 0x1800; GPU._objsize = (val & 0x04) != 0 ? 1 : 0; GPU._objon = (val & 0x02) != 0 ? 1 : 0; GPU._bgon = (val & 0x01) != 0 ? 1 : 0; break; case 2: GPU._yscrl = val; break; case 3: GPU._xscrl = val; break; case 5: GPU._raster = val; goto case 6; // OAM DMA case 6: int v; for (var i = 0; i < 160; i++) { v = MMU.rb((val << 8) + i); GPU._oam[i] = v; GPU.updateoam(0xFE00 + i, v); } break; // BG palette mapping case 7: for (var i = 0; i < 4; i++) { switch ((val >> (i * 2)) & 3) { case 0: GPU._palette.bg[i] = 255; break; case 1: GPU._palette.bg[i] = 192; break; case 2: GPU._palette.bg[i] = 96; break; case 3: GPU._palette.bg[i] = 0; break; } } break; // OBJ0 palette mapping case 8: for (var i = 0; i < 4; i++) { switch ((val >> (i * 2)) & 0b11) { case 0: GPU._palette.obj0[i] = 255; break; case 1: GPU._palette.obj0[i] = 192; break; case 2: GPU._palette.obj0[i] = 96; break; case 3: GPU._palette.obj0[i] = 0; break; } } break; // OBJ1 palette mapping case 9: for (var i = 0; i < 4; i++) { switch ((val >> (i * 2)) & 0b11) { case 0: GPU._palette.obj1[i] = 255; break; case 1: GPU._palette.obj1[i] = 192; break; case 2: GPU._palette.obj1[i] = 96; break; case 3: GPU._palette.obj1[i] = 0; break; } } break; } }
public static int rw(int addr) { return(MMU.rb(addr) + (MMU.rb(addr + 1) << 8)); }
public static void exec() { Z80._r.r = (Z80._r.r + 1) & 127; Z80._map[MMU.rb(Z80._r.pc++)](); Z80._clock.m += Z80._r.m; }