public void CreateRAM(int addrWidth, int dataWidth, int capacity, int readLatency, int writeLatency,
out Component part, out IRAM ram)
{
if (writeLatency != 1)
throw new NotSupportedException();
bool regPrim, regOut;
switch (readLatency)
{
case 1:
regPrim = false;
regOut = false;
break;
case 2:
regPrim = true;
regOut = false;
break;
case 3:
regPrim = true;
regOut = true;
break;
default:
throw new NotSupportedException();
}
BlockMem bmem = new BlockMem()
{
IPAlgorithm = BlockMem.EIPAlgorithm.MinimumArea,
AssumeSynchronousClk = false,
ECC = false,
ECCType = BlockMem.EECCType.NoECC,
EnableA = BlockMem.EENAUsage.UseENAPin,
EnableB = BlockMem.EENBUsage.AlwaysEnabled,
ErrorInjectionType = BlockMem.EErrorInjectionType.SingleBitErrorInjection,
MemoryType = BlockMem.EMemoryType.SinglePortRAM,
OperatingModeA = BlockMem.EOperatingMode.WriteFirst,
OperatingModeB = BlockMem.EOperatingMode.WriteFirst,
PipelineStages = 0,
ReadWidthA = dataWidth,
ReadWidthB = dataWidth,
RegisterPortAInputOfSoftECC = false,
RegisterPortAOutputOfMemoryCore = regOut,
RegisterPortAOutputOfMemoryPrimitives = regPrim,
RegisterPortBOutputOfMemoryCore = false,
RegisterPortBOutputOfMemoryPrimitives = false,
RegisterPortBOutputOfSoftECC = false,
ResetMemoryLatchA = false,
ResetMemoryLatchB = false,
ResetPriorityA = BlockMem.EResetPriority.CE,
ResetPriorityB = BlockMem.EResetPriority.CE,
ResetType = BlockMem.EResetType.Sync,
SoftECC = false,
UseByteWriteEnable = false,
UseErrorInjectionPins = false,
UseRegCeAPin = false,
UseRegCeBPin = false,
UseRstAPin = false,
UseRstBPin = false,
WriteDepthA = MathExt.CeilPow2(capacity),
WriteWidthA = dataWidth,
WriteWidthB = dataWidth
};
part = bmem;
ram = bmem.SideA;
}
public MemoryTransactor(BlockMem mem, ETAGroup group):
base(mem)
{
_mem = mem;
_name = group.ToString();
_group = group;
}
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj)
{
MemoryRegion region = null;
IXilinxBlockMemSide side = null;
Unsigned fixAddr = Unsigned.FromUInt(0, 1);
switch (instr.Name)
{
case InstructionCodes.RdMem:
case InstructionCodes.WrMem:
region = instr.Operand as MemoryRegion;
side = instr.Operand as IXilinxBlockMemSide;
break;
case InstructionCodes.RdMemFix:
case InstructionCodes.WrMemFix:
{
var tup = ((Tuple<MemoryRegion, Unsigned>)instr.Operand);
region = tup.Item1;
fixAddr = tup.Item2;
}
break;
default:
return null;
}
if (side == null &&
region != _region)
return null;
if (side == null)
{
var bmem = new BlockMem()
{
IPAlgorithm = BlockMem.EIPAlgorithm.MinimumArea,
AssumeSynchronousClk = true,
ECC = false,
ECCType = BlockMem.EECCType.NoECC,
EnableA = BlockMem.EENAUsage.AlwaysEnabled,
EnableB = BlockMem.EENBUsage.AlwaysEnabled,
ErrorInjectionType = BlockMem.EErrorInjectionType.SingleBitErrorInjection,
MemoryType = BlockMem.EMemoryType.SinglePortRAM,
OperatingModeA = BlockMem.EOperatingMode.WriteFirst,
OperatingModeB = BlockMem.EOperatingMode.WriteFirst,
PipelineStages = 1,
ReadWidthA = (int)region.MarshalInfo.WordSize,
ReadWidthB = (int)region.MarshalInfo.WordSize,
RegisterPortAInputOfSoftECC = false,
RegisterPortAOutputOfMemoryCore = false,
RegisterPortAOutputOfMemoryPrimitives = false,
RegisterPortBOutputOfMemoryCore = false,
RegisterPortBOutputOfMemoryPrimitives = false,
RegisterPortBOutputOfSoftECC = false,
ResetMemoryLatchA = false,
ResetMemoryLatchB = false,
ResetPriorityA = BlockMem.EResetPriority.CE,
ResetPriorityB = BlockMem.EResetPriority.CE,
ResetType = BlockMem.EResetType.Sync,
SoftECC = false,
UseByteWriteEnable = false,
UseErrorInjectionPins = false,
UseRegCeAPin = false,
UseRegCeBPin = false,
UseRstAPin = false,
UseRstBPin = false,
WriteDepthA = MathExt.CeilPow2((int)region.RequiredSize),
WriteWidthA = (int)region.MarshalInfo.WordSize,
WriteWidthB = (int)region.MarshalInfo.WordSize
};
foreach (MemoryMappedStorage mms in region.Items)
{
if (mms.Data != null)
{
StdLogicVector[] data = mms.Layout.SerializeInstance(mms.Data);
StdLogicVector addr = mms.BaseAddress.SLVValue;
foreach (StdLogicVector dataWord in data)
{
bmem.InitialWrite(addr, dataWord);
addr += "1";
}
}
}
side = bmem.SideA;
}
switch (instr.Name)
{
case InstructionCodes.RdMem:
return new BlockMemReadMapping(side);
case InstructionCodes.RdMemFix:
return new BlockMemReadFixMapping(side, fixAddr);
case InstructionCodes.WrMem:
return new BlockMemWriteMapping(side);
case InstructionCodes.WrMemFix:
return new BlockMemWriteFixMapping(side, fixAddr);
default:
throw new NotImplementedException();
}
}