public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xA3, 0x4, true, true, false, false, false, false, true, false, cmask: 4)); // no execute Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xA3, 0x6, true, true, false, false, false, false, true, false, cmask: 6)); // LDM pending Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xA3, 0xC, true, true, false, false, false, false, true, false, cmask: 0xC)); // L1D pending, pmc2 only Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xA3, 0x5, true, true, false, false, false, false, true, false, cmask: 5)); // L2 Pending } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x80, 0x1, true, true, false, false, false, false, true, false, 0)); // ic hit Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x80, 0x2, true, true, false, false, false, false, true, false, 0)); // ic miss Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x80, 0x4, true, true, false, false, false, false, true, false, 0)); // ifetch stall Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x87, 0x4, true, true, false, false, false, false, true, false, 0)); // iq full } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // PMC0 - all uops issued across both threads, cmask 1 Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xE, 0x1, true, true, false, false, false, anyThread: true, true, false, cmask: 1)); Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xE, 0x1, true, true, false, false, false, anyThread: true, true, false, cmask: 2)); Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xE, 0x1, true, true, false, false, false, anyThread: true, true, false, cmask: 3)); Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xE, 0x1, true, true, false, false, false, anyThread: true, true, false, cmask: 4)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to count l2 references Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x24, 0xFF, true, true, false, false, false, false, true, false, 0)); // Set PMC1 to count l2 misses Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x24, 0x3F, true, true, false, false, false, false, true, false, 0)); // Set PMC2 to count L2 lines in Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xF1, 0x7, true, true, false, false, false, false, true, false, 0)); // Set PMC3 to count dirty L2 lines evicted Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xF2, 0x6, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // PMC0 - all retired loads Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xD0, 0x82, true, true, false, false, false, false, true, false, 0)); // PMC1 - L1 miss Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xD1, 0x8, true, true, false, false, false, false, true, false, 0)); // PMC2 - L2 miss Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xD1, 0x10, true, true, false, false, false, false, true, false, 0)); // PMC3 - L3 miss Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xD1, 0x20, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to count eliminated integer move elim candidates Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x58, 0x1, true, true, false, false, false, false, true, false, 0)); // Set PMC1 to count eliminated simd move elim candidates Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x58, 0x2, true, true, false, false, false, false, true, false, 0)); // Set PMC2 to count not eliminated int move candidates Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x58, 0x4, true, true, false, false, false, false, true, false, 0)); // Set PMC3 to count not eliminated simd move candidates Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x58, 0x8, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to count page walk duration Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0x08, 0x10, true, true, false, false, false, false, true, false, 0)); // Set PMC1 to count DTLB miss -> STLB hit Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0x08, 0x60, true, true, false, false, false, false, true, false, 0)); // Set PMC2 to DTLB misses that cause walks Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0x08, 0x1, true, true, false, false, false, false, true, false, 0)); // Set PMC3 to count completed walks Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0x08, 0xE, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to cycles when uops are executed on port 0 // anyThread sometimes works (i7-4712HQ) and sometimes not (E5-1620v3). It works on SNB. // don't set anythread for consistent behavior Ring0.WriteMsr(IA32_PERFEVTSEL0, GetPerfEvtSelRegisterValue(0xA1, 0x01, usr: true, os: true, edge: false, pc: false, interrupt: false, anyThread: false, enable: true, invert: false, cmask: 0)); // Set PMC1 to count ^ for port 1 Ring0.WriteMsr(IA32_PERFEVTSEL1, GetPerfEvtSelRegisterValue(0xA1, 0x02, true, true, false, false, false, false, true, false, 0)); // Set PMC2 to count ^ for port 5 Ring0.WriteMsr(IA32_PERFEVTSEL2, GetPerfEvtSelRegisterValue(0xA1, 0x20, true, true, false, false, false, false, true, false, 0)); // Set PMC3 to count ^ for port 6 Ring0.WriteMsr(IA32_PERFEVTSEL3, GetPerfEvtSelRegisterValue(0xA1, 0x40, true, true, false, false, false, false, true, false, 0)); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to count all rename stalls because of back pressure ulong lbFull = GetPerfEvtSelRegisterValue(0xA2, 0x01, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL0, lbFull); // Set PMC1 ^^ SB full ulong sbFull = GetPerfEvtSelRegisterValue(0xA2, 0x08, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL1, sbFull); // Set PMC2 ^^ RS full ulong rsFull = GetPerfEvtSelRegisterValue(0xA2, 0x04, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL2, rsFull); // Set PMC3 ^^ ROB full ulong robFull = GetPerfEvtSelRegisterValue(0xA2, 0x10, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL3, robFull); } }
public void Initialize() { cpu.EnablePerformanceCounters(); for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++) { ThreadAffinity.Set(1UL << threadIdx); // Set PMC0 to cycles when uops are executed on port 2 ulong p2Ops = GetPerfEvtSelRegisterValue(0xA1, 0x04, usr: true, os: true, edge: false, pc: false, interrupt: false, anyThread: false, enable: true, invert: false, cmask: 0); Ring0.WriteMsr(IA32_PERFEVTSEL0, p2Ops); // Set PMC1 to count ^ for port 3 ulong p3Ops = GetPerfEvtSelRegisterValue(0xA1, 0x08, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL1, p3Ops); // Set PMC2 to count ^ for port 4 ulong p4Ops = GetPerfEvtSelRegisterValue(0xA1, 0x10, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL2, p4Ops); // Set PMC3 to count ^ for port 7 ulong p7Ops = GetPerfEvtSelRegisterValue(0xA1, 0x80, true, true, false, false, false, false, true, false, 0); Ring0.WriteMsr(IA32_PERFEVTSEL3, p7Ops); } }