Esempio n. 1
0
            public void Initialize()
            {
                cpu.EnablePerformanceCounters();
                for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++)
                {
                    ThreadAffinity.Set(1UL << threadIdx);
                    // PERF_CTR0 = active cycles
                    Ring0.WriteMsr(MSR_PERF_CTL_0, GetPerfCtlValue(0x76, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR1 = retired instructions
                    Ring0.WriteMsr(MSR_PERF_CTL_1, GetPerfCtlValue(0xC0, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR2 to count retired branches
                    Ring0.WriteMsr(MSR_PERF_CTL_2, GetPerfCtlValue(0xC2, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR3 = mispredicted retired branches
                    Ring0.WriteMsr(MSR_PERF_CTL_3, GetPerfCtlValue(0xC3, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR4 = L1 BTB Overrides
                    Ring0.WriteMsr(MSR_PERF_CTL_4, GetPerfCtlValue(0x8A, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR5 = L2 BTB overrides
                    Ring0.WriteMsr(MSR_PERF_CTL_5, GetPerfCtlValue(0x8B, 0, true, true, false, false, true, false, 0, 0, false, false));
                }
            }
Esempio n. 2
0
            public void Initialize()
            {
                cpu.EnablePerformanceCounters();
                for (int threadIdx = 0; threadIdx < cpu.GetThreadCount(); threadIdx++)
                {
                    ThreadAffinity.Set(1UL << threadIdx);
                    // PERF_CTR2 = active cycles
                    Ring0.WriteMsr(MSR_PERF_CTL_0, GetPerfCtlValue(0x76, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR3 = ret instr
                    Ring0.WriteMsr(MSR_PERF_CTL_1, GetPerfCtlValue(0xC0, 0, true, true, false, false, true, false, 0, 0, false, false));

                    // Set PERF_CTR2 to count DC reflls from L2
                    Ring0.WriteMsr(MSR_PERF_CTL_2, GetPerfCtlValue(0x43, 1, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR3 = DC refills from another cache (L3)
                    Ring0.WriteMsr(MSR_PERF_CTL_3, GetPerfCtlValue(0x43, 2, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR4 = DC refills  from local dram
                    Ring0.WriteMsr(MSR_PERF_CTL_4, GetPerfCtlValue(0x43, 8, true, true, false, false, true, false, 0, 0, false, false));

                    // PERF_CTR5 = remote refills
                    Ring0.WriteMsr(MSR_PERF_CTL_5, GetPerfCtlValue(0x43, 0x50, true, true, false, false, true, false, 0, 0, false, false));
                }
            }