void SetVRAM()
{
int[] bank = new int[4];
for (int i = 0; i < 4; i++)
{
bank[i] = (nth_reg[i] << 8) | (ntl_reg[i]);
}
if (mir_mode != 0)
{
for (int i = 0; i < 4; i++)
{
if ((nth_reg[i] == 0) && (ntl_reg[i] == (byte)i))
{
mir_mode = 0;
}
}
if (mir_mode != 0)
{
mem.Switch1kCHRToVRAM(bank[0], 0);
mem.Switch1kCHRToVRAM(bank[1], 1);
mem.Switch1kCHRToVRAM(bank[2], 2);
mem.Switch1kCHRToVRAM(bank[3], 3);
}
}
else
{
if (mir_type == 0)
{
mem.Cartridge.Mirroring = Mirroring.Vertical;
mem.ApplayMirroring();
}
else if (mir_type == 1)
{
mem.Cartridge.Mirroring = Mirroring.Horizontal;
mem.ApplayMirroring();
}
else
{
mem.Cartridge.Mirroring = Mirroring.One_Screen;
mem.Cartridge.MirroringBase = 0x2000;
mem.ApplayMirroring();
}
}
}
public void Write(ushort address, byte data)
{
/*IRQ controls*/
if (address >= 0x5000 & address <= 0x57FF)
{
irq_counter = (short)((irq_counter & 0xFF00) | data);
}
else if (address >= 0x5800 & address <= 0x5FFF)
{
IRQEnabled = (data & 0x80) != 0;
irq_counter = (short)((irq_counter & 0x00FF) | (data & 0x7F) << 8);
}
/*Pattern Table Control*/
else if (address >= 0x8000 & address <= 0x87FF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 0);
}
else
{
Map.Switch1kCRAM(data, 0);
}
}
else if (address >= 0x8800 & address <= 0x8FFF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 1);
}
else
{
Map.Switch1kCRAM(data, 1);
}
}
else if (address >= 0x9000 & address <= 0x97FF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 2);
}
else
{
Map.Switch1kCRAM(data, 2);
}
}
else if (address >= 0x9800 & address <= 0x9FFF)
{
if (!VROMRAMfor0000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 3);
}
else
{
Map.Switch1kCRAM(data, 3);
}
}
else if (address >= 0xA000 & address <= 0xA7FF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 4);
}
else
{
Map.Switch1kCRAM(data, 4);
}
}
else if (address >= 0xA800 & address <= 0xAFFF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 5);
}
else
{
Map.Switch1kCRAM(data, 5);
}
}
else if (address >= 0xB000 & address <= 0xB7FF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 6);
}
else
{
Map.Switch1kCRAM(data, 6);
}
}
else if (address >= 0xB800 & address <= 0xBFFF)
{
if (!VROMRAMfor1000 | data < 0xE0)
{
Map.Switch1kChrRom(data, 7);
}
else
{
Map.Switch1kCRAM(data, 7);
}
}
/*Name Table Control*/
else if (address >= 0xC000 & address <= 0xC7FF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 0);
}
else
{
Map.SwitchVRAMToVRAM(data, 0);
}
}
else if (address >= 0xC800 & address <= 0xCFFF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 1);
}
else
{
Map.SwitchVRAMToVRAM(data, 1);
}
}
else if (address >= 0xD000 & address <= 0xD7FF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 2);
}
else
{
Map.SwitchVRAMToVRAM(data, 2);
}
}
else if (address >= 0xD800 & address <= 0xDFFF)
{
if (data < 0xE0)
{
Map.Switch1kCHRToVRAM(data, 3);
}
else
{
Map.SwitchVRAMToVRAM(data, 3);
}
}
/*CPU Memory Control*/
else if (address >= 0xE000 & address <= 0xE7FF)
{
Map.Switch8kPrgRom(data * 2, 0);
}
else if (address >= 0xE800 & address <= 0xEFFF)
{
if (address == 0xE800)
{
VROMRAMfor0000 = (data & 0x40) == 0x40;
VROMRAMfor1000 = (data & 0x80) == 0x80;
}
Map.Switch8kPrgRom(data * 2, 1);
}
else if (address >= 0xF000 & address <= 0xF7FF)
{
Map.Switch8kPrgRom(data * 2, 2);
}
}