public void add_to_cache_queue(Req req)
{
req.ts_departure = (long)(cycles + (ulong)Config.cache_hit_latency);
cache_hit_queue.AddLast(req);
inst_wnd.add(req.block_addr, true, false, req.pc);
return;
}
public void issue_insts(bool issued_rd_req)
{
//issue instructions
for (int i = 0; i < Config.proc.ipc; i++)
{
if (inst_wnd.is_full())
{
if (i == 0)
{
Stat.procs[pid].stall_inst_wnd.Collect();
// Measurement.core_stall_cycles[pid] += 1;
}
return;
}
//cpu instructions
if (curr_cpu_inst_cnt > 0)
{
curr_cpu_inst_cnt--;
inst_wnd.add(0, false, true);
continue;
}
//only one memory instruction can be issued per cycle
if (issued_rd_req)
{
return;
}
//memory instruction (only AFTER checking for one memory instruction per cycle)
inst_wnd.add(curr_rd_req.block_addr, true, false);
//check if true miss
bool false_miss = inst_wnd.is_duplicate(curr_rd_req.block_addr);
if (false_miss)
{
Dbg.Assert(curr_rd_req.wb_req == null);
RequestPool.enpool(curr_rd_req);
curr_rd_req = get_req();
continue;
}
//try mshr
bool mshr_ok = insert_mshr(curr_rd_req);
if (!mshr_ok)
{
mshr_retry = true;
return;
}
//try memory controller
bool mctrl_ok = insert_mctrl(curr_rd_req);
if (!mctrl_ok)
{
mctrl_retry = true;
return;
}
//issued memory request
issued_rd_req = true;
//get new read request
curr_rd_req = get_req();
}
}