protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Cpu, machineCycle, Registers.SP);
return(_instructionM2);
case MachineCycleNames.M3:
_instructionM3 = new ReadT3InstructionPart(Cpu, machineCycle, (ushort)(Registers.SP + 1));
return(_instructionM3);
case MachineCycleNames.M4:
return(new WriteT3InstructionPart(Cpu, machineCycle, Registers.SP)
{
Data = new OpcodeByte(GetValueLo())
});
case MachineCycleNames.M5:
return(new WriteT3InstructionPart(Cpu, machineCycle, (ushort)(Registers.SP + 1))
{
Data = new OpcodeByte(GetValueHi())
});
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
private CpuState CreateInstructionPartM4()
{
ushort address = GetAddress();
if (IsWrite)
{
return(new WriteT3InstructionPart(Cpu, MachineCycleNames.M4, address)
{
Data = new OpcodeByte(GetValueLo())
});
}
_readInstructionLo = new ReadT3InstructionPart(Cpu, MachineCycleNames.M4, address);
return(_readInstructionLo);
}
private CpuState CreateInstructionPartM5()
{
ushort address = (ushort)(GetAddress() + 1);
if (IsWrite)
{
return(new WriteT3InstructionPart(Cpu, MachineCycleNames.M5, address)
{
Data = new OpcodeByte(GetValueHi())
});
}
_readInstructionHi = new ReadT3InstructionPart(Cpu, MachineCycleNames.M5, address);
return(_readInstructionHi);
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Cpu, machineCycle, GetAddress());
return(_instructionM2);
case MachineCycleNames.M3:
_instructionM3 = new WriteT3InstructionPart(Cpu, machineCycle, GetAddress());
_instructionM3.Data = IncDecValue(_instructionM2.Data);
return(_instructionM3);
default:
throw Errors.InvalidMachineCycle(machineCycle);
}
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
var regA = ExecutionEngine.Opcode.Definition.P == 3;
switch (machineCycle)
{
case MachineCycleNames.M4:
_instructionM4 = new ReadT3InstructionPart(Die, machineCycle, GetAddress());
return(_instructionM4);
case MachineCycleNames.M5:
if (regA)
{
throw Errors.AssignedToIllegalOpcode();
}
_instructionM5 = new ReadT3InstructionPart(Die, machineCycle, (ushort)(GetAddress() + 1));
return(_instructionM5);
}
return(base.GetInstructionPart(machineCycle));
}
protected override CpuState GetInstructionPart(MachineCycleNames machineCycle)
{
switch (machineCycle)
{
case MachineCycleNames.M2:
_instructionM2 = new ReadT3InstructionPart(Die, machineCycle, _address);
return(_instructionM2);
case MachineCycleNames.M3:
if (IsBitInstruction)
{
throw Errors.AssignedToIllegalOpcode();
}
return(new WriteT3InstructionPart(Die, machineCycle, _address)
{
Data = new OpcodeByte(GetValue())
});
default:
throw Errors.AssignedToIllegalOpcode();
}
}
private ReadT3InstructionPart CreateReadAddressInstructionPart(MachineCycleNames machineCycle)
{
_readPart = new ReadT3InstructionPart(Cpu, machineCycle, GetAddress());
return(_readPart);
}
private CpuState CreateReadIndirectPart(MachineCycleNames machineCycle)
{
_readIndirectPart = new Instructions.ReadT3InstructionPart(Die, machineCycle);
return(_readIndirectPart);
}
