public void execute(ExecuteArgs args) { if(args.locked == false) { registerWB = 0; switch (args.op) { case 1: //LDA registerTEMP = args.value; break; case 2: //STA registerTEMP = args.acc; // mem registerWB = 1; break; case 3: //ADD registerWB = 0; registerTEMP = (short)(args.acc + args.value); break; case 4: //SUB registerWB = 0; registerTEMP = (short)(args.acc - args.value); //imm break; case 5: //MUL registerWB = 0; registerTEMP = (short)(args.acc * args.value); //imm delaySlots += 4; break; case 6: //DIV registerWB = 0; registerTEMP = (short)(args.acc / args.value); //imm delaySlots += 4; break; case 7: //AND registerWB = 0; registerTEMP = (short)(args.acc & args.value); //imm break; case 8: //OR registerWB = 0; registerTEMP = (short)(args.acc | args.value); //imm break; case 9: //SHL registerWB = 0; registerTEMP = (short)(args.acc << args.value); break; case 10: //NOTA registerWB = 0; registerTEMP = (short)~args.acc; break; case 11: //BA registerTEMP = (short)(args.value); registerWB = 2; break; case 12: //BE if (registerACC == 0) { registerTEMP = (short)(args.value); } registerWB = 2; break; case 13: //BL if (registerACC < 0) { registerTEMP = (short)(args.value); } registerWB = 2; break; case 14: //BG if (registerACC > 0) { registerTEMP = (short)(args.value); } registerWB = 2; break; case 15: //NOP registerWB = -1; break; case 16: //HLT registerWB = -1; registerPC = 0; fakePC = 0; break; } } }
public void stepPipeline(FetchArgs fetchArgs,DecodeArgs decodeArgs,ExecuteArgs executeArgs, WritebackArgs writebackArgs) { Thread f = new Thread(() => fetch(fetchArgs)); Thread d = new Thread(() => decode(decodeArgs)); Thread e = new Thread(() => execute(executeArgs)); Thread w = new Thread(() => writeback(writebackArgs)); f.Start(); d.Start(); e.Start(); w.Start(); f.Join(); d.Join(); e.Join(); w.Join(); }