public static void RunTest()
{
DesignContext.Reset();
TestHLS_Cordic_Testbench tb = new TestHLS_Cordic_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_Cordic", "TestHLS_Cordic");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
//project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);;
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_CFlow2_Testbench tb = new TestHLS_CFlow2_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX75T_FF484 fpga = new XC6VLX75T_FF484()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = tb.DUT
};
fpga.Testbenches.Add(tb);
fpga.Synthesize(@".\hdl_out_TestHLS_CFlow2", "TestHLS_CFlow2");
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_CFlow2\doc"));
eng.Synthesize(new DocumentationGenerator());
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalArithSizingMode = EArithSizingMode.VHDLCompliant;
var a = SFix.FromDouble(1.0, 8, 10);
var b = SFix.FromDouble(2.0, 8, 10);
var c = SFix.FromDouble(3.0, 8, 10);
var d = SFix.FromDouble(4.0, 8, 10);
TestAddMul2 dut = new TestAddMul2()
{
Clk = new SLSignal(),
A = new Signal <SFix>()
{
InitialValue = a
},
B = new Signal <SFix>()
{
InitialValue = b
},
C = new Signal <SFix>()
{
InitialValue = c
},
D = new Signal <SFix>()
{
InitialValue = d
},
R = new Signal <SFix>()
{
InitialValue = a * b + c * d
}
};
DesignContext.Instance.Elaborate();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = dut
};
fpga.Synthesize(@".\hdl_out_TestAddMul2", "TestAddMul2");
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalArithSizingMode = EArithSizingMode.InSizeIsOutSize;
var design = new TestHLS_SFixDiv(8, 32);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = design
};
fpga.Testbenches.Add(design);
fpga.Synthesize(@".\hdl_out_TestHLS_SFixDiv", "TestHLS_SFixDiv");
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_VanDerPol_Testbench tb = new TestHLS_VanDerPol_Testbench();
DesignContext.Instance.Elaborate();
//DesignContext.Instance.Simulate(new Time(4.0, ETimeUnit.us));
//DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = tb.DUT
};
fpga.Testbenches.Add(tb);
fpga.Pins["J9"].Map(tb.DUT.Clk);
fpga.Synthesize(@".\hdl_out_TestHLS_VanDerPol", "TestHLS_VanDerPol");
}
