public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
var rtlInstrs = new List <RtlInstruction>();
this.m = new RtlEmitter(rtlInstrs);
this.rtlc = RtlClass.Linear;
switch (instr.Opcode)
{
case Opcode.mov:
case Opcode.rev:
case Opcode.revw:
case Opcode.tbl:
host.Warn(
instr.Address,
"M6812 instruction '{0}' is not supported yet.",
instr.Opcode);
goto case Opcode.invalid;
case Opcode.invalid:
this.rtlc = RtlClass.Invalid;
m.Invalid();
break;
case Opcode.aba: RewriteAba(); break;
case Opcode.adca: RewriteAdcSbc(Registers.a, m.IAdd); break;
case Opcode.adcb: RewriteAdcSbc(Registers.b, m.IAdd); break;
case Opcode.adda: RewriteArithmetic(Registers.a, m.IAdd); break;
case Opcode.addb: RewriteArithmetic(Registers.b, m.IAdd); break;
case Opcode.addd: RewriteArithmetic(Registers.d, m.IAdd); break;
case Opcode.anda: RewriteLogical(Registers.a, m.And); break;
case Opcode.andb: RewriteLogical(Registers.b, m.And); break;
case Opcode.andcc: RewriteAndcc(); break;
case Opcode.asr: RewriteShiftMem(m.Sar); break;
case Opcode.asra: RewriteArithmetic(Registers.a, m.Sar); break;
case Opcode.asrb: RewriteArithmetic(Registers.b, m.Sar); break;
case Opcode.bcc: RewriteBcc(ConditionCode.UGE, FlagM.CF); break;
case Opcode.bclr: RewriteBclr(); break;
case Opcode.bcs: RewriteBcc(ConditionCode.ULT, FlagM.CF); break;
case Opcode.beq: RewriteBcc(ConditionCode.EQ, FlagM.ZF); break;
case Opcode.bge: RewriteBcc(ConditionCode.GE, FlagM.NF | FlagM.VF); break;
case Opcode.bgt: RewriteBcc(ConditionCode.GT, FlagM.NF | FlagM.VF | FlagM.ZF); break;
case Opcode.bhi: RewriteBcc(ConditionCode.UGT, FlagM.CF | FlagM.ZF); break;
case Opcode.ble: RewriteBcc(ConditionCode.LE, FlagM.NF | FlagM.VF | FlagM.ZF); break;
case Opcode.blt: RewriteBcc(ConditionCode.LT, FlagM.CF | FlagM.ZF); break;
case Opcode.bls: RewriteBcc(ConditionCode.ULE, FlagM.VF | FlagM.ZF); break;
case Opcode.bmi: RewriteBcc(ConditionCode.LT, FlagM.NF); break;
case Opcode.bne: RewriteBcc(ConditionCode.NE, FlagM.ZF); break;
case Opcode.bpl: RewriteBcc(ConditionCode.GT, FlagM.NF); break;
case Opcode.bvc: RewriteBcc(ConditionCode.NO, FlagM.VF); break;
case Opcode.bvs: RewriteBcc(ConditionCode.OV, FlagM.VF); break;
case Opcode.bgnd: RewriteBgnd(); break;
case Opcode.bita: RewriteBit(Registers.a); break;
case Opcode.bitb: RewriteBit(Registers.b); break;
case Opcode.bra: RewriteBra(); break;
case Opcode.brclr: RewriteBrclr(); break;
case Opcode.brn: m.Nop(); break;
case Opcode.brset: RewriteBrset(); break;
case Opcode.bset: RewriteBset(); break;
case Opcode.bsr: RewriteBsr(); break;
case Opcode.call: RewriteCall(); break;
case Opcode.cba: RewriteCba(); break;
case Opcode.clr: RewriteClr(); break;
case Opcode.clra: RewriteClr(Registers.a); break;
case Opcode.clrb: RewriteClr(Registers.b); break;
case Opcode.cmpa: RewriteCmp(Registers.a); break;
case Opcode.cmpb: RewriteCmp(Registers.b); break;
case Opcode.com: RewriteCom(); break;
case Opcode.coma: RewriteCom(Registers.a); break;
case Opcode.comb: RewriteCom(Registers.b); break;
case Opcode.cpd: RewriteCmp(Registers.d); break;
case Opcode.cps: RewriteCmp(Registers.sp); break;
case Opcode.cpx: RewriteCmp(Registers.x); break;
case Opcode.cpy: RewriteCmp(Registers.y); break;
case Opcode.daa: RewriteDaa(); break;
case Opcode.dbeq: RewriteDb(m.Eq0); break;
case Opcode.dbne: RewriteDb(m.Ne0); break;
case Opcode.dec: RewriteIncDec(m.ISub); break;
case Opcode.deca: RewriteIncDec(Registers.a, m.ISub); break;
case Opcode.decb: RewriteIncDec(Registers.b, m.ISub); break;
case Opcode.dex: RewriteIncDecXY(Registers.x, m.ISub); break;
case Opcode.dey: RewriteIncDecXY(Registers.y, m.ISub); break;
case Opcode.ediv: RewriteEdiv(m.UDiv, m.Remainder); break;
case Opcode.edivs: RewriteEdiv(m.SDiv, m.Remainder); break;
case Opcode.emacs: RewriteEmacs(); break;
case Opcode.emaxd: RewriteEmaxmind("__umax"); break;
case Opcode.emaxm: RewriteEmaxminm("__umax"); break;
case Opcode.emind: RewriteEmaxmind("__umin"); break;
case Opcode.eminm: RewriteEmaxminm("__umin"); break;
case Opcode.emul: RewriteEmul(m.UMul); break;
case Opcode.emuls: RewriteEmul(m.SMul); break;
case Opcode.eora: RewriteLogical(Registers.a, m.Xor); break;
case Opcode.eorb: RewriteLogical(Registers.b, m.Xor); break;
case Opcode.etbl: RewriteEtbl(); break;
case Opcode.fdiv: RewriteFdiv(); break;
case Opcode.ibeq: RewriteIb(m.Eq0); break;
case Opcode.ibne: RewriteIb(m.Ne0); break;
case Opcode.idiv: RewriteIdiv(m.UDiv); break;
case Opcode.idivs: RewriteIdiv(m.SDiv); break;
case Opcode.inc: RewriteIncDec(m.IAdd); break;
case Opcode.inca: RewriteIncDec(Registers.a, m.IAdd); break;
case Opcode.incb: RewriteIncDec(Registers.b, m.IAdd); break;
case Opcode.inx: RewriteIncDecXY(Registers.x, m.IAdd); break;
case Opcode.iny: RewriteIncDecXY(Registers.y, m.IAdd); break;
case Opcode.jmp: RewriteJmp(); break;
case Opcode.jsr: RewriteJsr(); break;
case Opcode.lbcc: RewriteBcc(ConditionCode.UGE, FlagM.CF); break;
case Opcode.lbcs: RewriteBcc(ConditionCode.ULT, FlagM.CF); break;
case Opcode.lbeq: RewriteBcc(ConditionCode.EQ, FlagM.ZF); break;
case Opcode.lbge: RewriteBcc(ConditionCode.GE, FlagM.NF | FlagM.VF); break;
case Opcode.lbgt: RewriteBcc(ConditionCode.GT, FlagM.NF | FlagM.VF | FlagM.ZF); break;
case Opcode.lbhi: RewriteBcc(ConditionCode.UGT, FlagM.CF | FlagM.ZF); break;
case Opcode.lble: RewriteBcc(ConditionCode.LE, FlagM.NF | FlagM.VF | FlagM.ZF); break;
case Opcode.lblt: RewriteBcc(ConditionCode.LT, FlagM.CF | FlagM.ZF); break;
case Opcode.lbls: RewriteBcc(ConditionCode.ULE, FlagM.VF | FlagM.ZF); break;
case Opcode.lbmi: RewriteBcc(ConditionCode.LT, FlagM.NF); break;
case Opcode.lbne: RewriteBcc(ConditionCode.NE, FlagM.ZF); break;
case Opcode.lbpl: RewriteBcc(ConditionCode.GT, FlagM.NF); break;
case Opcode.lbra: RewriteBra(); break;
case Opcode.lbrn: m.Nop(); break;
case Opcode.lbvc: RewriteBcc(ConditionCode.NO, FlagM.VF); break;
case Opcode.lbvs: RewriteBcc(ConditionCode.OV, FlagM.VF); break;
case Opcode.ldaa: RewriteLd(Registers.a); break;
case Opcode.ldab: RewriteLd(Registers.b); break;
case Opcode.ldd: RewriteLd(Registers.d); break;
case Opcode.lds: RewriteLd(Registers.sp); break;
case Opcode.ldx: RewriteLd(Registers.x); break;
case Opcode.ldy: RewriteLd(Registers.y); break;
case Opcode.leas: RewriteLea(Registers.sp); break;
case Opcode.leax: RewriteLea(Registers.x); break;
case Opcode.leay: RewriteLea(Registers.y); break;
case Opcode.lsl: RewriteShiftMem(m.Shl); break;
case Opcode.lsla: RewriteArithmetic(Registers.a, m.Shl); break;
case Opcode.lslb: RewriteArithmetic(Registers.b, m.Shl); break;
case Opcode.lsld: RewriteArithmetic(Registers.d, m.Shl); break;
case Opcode.lsr: RewriteShiftMem(m.Shr); break;
case Opcode.lsra: RewriteArithmetic(Registers.a, m.Shr); break;
case Opcode.lsrb: RewriteArithmetic(Registers.b, m.Shr); break;
case Opcode.lsrd: RewriteArithmetic(Registers.d, m.Shr); break;
case Opcode.maxa: RewriteMaxmina("__umax_b"); break;
case Opcode.maxm: RewriteMaxminm("__umax_b"); break;
case Opcode.mem: RewriteMem(); break;
case Opcode.mina: RewriteMaxmina("__umin_b"); break;
case Opcode.minm: RewriteMaxminm("__umin_b"); break;
case Opcode.mul: RewriteMul(); break;
case Opcode.neg: RewriteNeg(); break;
case Opcode.nega: RewriteNeg(Registers.a); break;
case Opcode.negb: RewriteNeg(Registers.b); break;
case Opcode.nop: m.Nop(); break;
case Opcode.oraa: RewriteLogical(Registers.a, m.Or); break;
case Opcode.orab: RewriteLogical(Registers.b, m.Or); break;
case Opcode.orcc: RewriteOrcc(); break;
case Opcode.psha: RewritePsh(Registers.a); break;
case Opcode.pshb: RewritePsh(Registers.b); break;
case Opcode.pshc: RewritePsh(Registers.ccr); break;
case Opcode.pshd: RewritePsh(Registers.d); break;
case Opcode.pshx: RewritePsh(Registers.x); break;
case Opcode.pshy: RewritePsh(Registers.y); break;
case Opcode.pula: RewritePul(Registers.a); break;
case Opcode.pulb: RewritePul(Registers.b); break;
case Opcode.pulc: RewritePul(Registers.ccr); break;
case Opcode.puld: RewritePul(Registers.d); break;
case Opcode.pulx: RewritePul(Registers.x); break;
case Opcode.puly: RewritePul(Registers.y); break;
case Opcode.rol: RewriteShiftMem(Rol); break;
case Opcode.rola: RewriteArithmetic(Registers.a, Rol); break;
case Opcode.rolb: RewriteArithmetic(Registers.b, Rol); break;
case Opcode.ror: RewriteShiftMem(Ror); break;
case Opcode.rora: RewriteArithmetic(Registers.a, Ror); break;
case Opcode.rorb: RewriteArithmetic(Registers.a, Ror); break;
case Opcode.rtc: RewriteRtc(); break;
case Opcode.rti: RewriteRti(); break;
case Opcode.rts: RewriteRts(); break;
case Opcode.sba: RewriteSba(); break;
case Opcode.sbca: RewriteAdcSbc(Registers.a, m.ISub); break;
case Opcode.sbcb: RewriteAdcSbc(Registers.b, m.ISub); break;
case Opcode.sex: RewriteSex(); break;
case Opcode.staa: RewriteSt(Registers.a); break;
case Opcode.stab: RewriteSt(Registers.b); break;
case Opcode.std: RewriteSt(Registers.d); break;
case Opcode.stop: RewriteStop(); break;
case Opcode.sts: RewriteSt(Registers.sp); break;
case Opcode.stx: RewriteSt(Registers.x); break;
case Opcode.sty: RewriteSt(Registers.y); break;
case Opcode.suba: RewriteSub(Registers.a); break;
case Opcode.subb: RewriteSub(Registers.b); break;
case Opcode.subd: RewriteSub(Registers.d); break;
case Opcode.swi: RewriteSwi(); break;
case Opcode.tab: RewriteTab(); break;
case Opcode.tba: RewriteTba(); break;
case Opcode.tbeq: RewriteTb(m.Eq0); break;
case Opcode.tbne: RewriteTb(m.Ne0); break;
case Opcode.tfr: RewriteTfr(); break;
case Opcode.trap: RewriteTrap(); break;
case Opcode.tst: RewriteTst(); break;
case Opcode.tsta: RewriteTst(Registers.a); break;
case Opcode.tstb: RewriteTst(Registers.b); break;
case Opcode.wai: RewriteWai(); break;
case Opcode.wav: RewriteWav(); break;
}
yield return(new RtlInstructionCluster(
instr.Address,
instr.Length,
rtlInstrs.ToArray())
{
Class = rtlc
});
}
}
private void Invalid()
{
m.Invalid();
rtlc = RtlClass.Invalid;
}
/// <summary>
/// Called when we need to generate an RtlBranch in the middle of an operation.
/// Normally, branches are at the end of the Rtl's of a translated instruction,
/// but in some cases, they are not.
/// </summary>
/// <param name="condition">Boolean expression</param>
/// <param name="target">Control goes to this address if condition is true</param>
/// <param name="rtlClass">Describes details the branch instruction</param>
/// <returns>A reference to this RtlEmitter.</returns>
public RtlBranch BranchInMiddleOfInstruction(Expression condition, Address target, RtlClass rtlClass)
{
var branch = new RtlBranch(condition, target, rtlClass);
branch.NextStatementRequiresLabel = true;
instrs.Add(branch);
return(branch);
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (instrs.MoveNext())
{
if (!instrs.Current.TryGetInternal(out this.instr))
{
continue;
throw new AddressCorrelatedException(
instrs.Current.Address,
"Invalid opcode cannot be rewritten to IR.");
}
this.ops = instr.ArchitectureDetail.Operands;
this.rtlInstructions = new List <RtlInstruction>();
this.rtlc = RtlClass.Linear;
this.m = new RtlEmitter(rtlInstructions);
switch (instr.Id)
{
default:
throw new AddressCorrelatedException(
instrs.Current.Address,
"Rewriting ARM Thumb opcode '{0}' ({1}) is not supported yet.",
instr.Mnemonic, instr.Id);
case ArmInstruction.ADD: RewriteBinop((a, b) => m.IAdd(a, b)); break;
case ArmInstruction.ADDW: RewriteAddw(); break;
case ArmInstruction.ADR: RewriteAdr(); break;
case ArmInstruction.AND: RewriteAnd(); break;
case ArmInstruction.ASR: RewriteShift(m.Sar); break;
case ArmInstruction.B: RewriteB(); break;
case ArmInstruction.BIC: RewriteBic(); break;
case ArmInstruction.BL: RewriteBl(); break;
case ArmInstruction.BLX: RewriteBlx(); break;
case ArmInstruction.BX: RewriteBx(); break;
case ArmInstruction.CBZ: RewriteCbnz(m.Eq0); break;
case ArmInstruction.CBNZ: RewriteCbnz(m.Ne0); break;
case ArmInstruction.CMP: RewriteCmp(); break;
case ArmInstruction.DMB: RewriteDmb(); break;
case ArmInstruction.EOR: RewriteEor(); break;
case ArmInstruction.IT: RewriteIt(); continue; // Don't emit anything yet.;
case ArmInstruction.LDR: RewriteLdr(PrimitiveType.Word32, PrimitiveType.Word32); break;
case ArmInstruction.LDRB: RewriteLdr(PrimitiveType.UInt32, PrimitiveType.Byte); break;
case ArmInstruction.LDRSB: RewriteLdr(PrimitiveType.Int32, PrimitiveType.SByte); break;
case ArmInstruction.LDREX: RewriteLdrex(); break;
case ArmInstruction.LDRH: RewriteLdr(PrimitiveType.UInt32, PrimitiveType.Word16); break;
case ArmInstruction.LSL: RewriteShift(m.Shl); break;
case ArmInstruction.LSR: RewriteShift(m.Shr); break;
case ArmInstruction.MOV: RewriteMov(); break;
case ArmInstruction.MOVT: RewriteMovt(); break;
case ArmInstruction.MOVW: RewriteMovw(); break;
case ArmInstruction.MRC: RewriteMrc(); break;
case ArmInstruction.MVN: RewriteMvn(); break;
case ArmInstruction.POP: RewritePop(); break;
case ArmInstruction.PUSH: RewritePush(); break;
case ArmInstruction.RSB: RewriteRsb(); break;
case ArmInstruction.STM: RewriteStm(); break;
case ArmInstruction.STR: RewriteStr(PrimitiveType.Word32); break;
case ArmInstruction.STRH: RewriteStr(PrimitiveType.Word16); break;
case ArmInstruction.STRB: RewriteStr(PrimitiveType.Byte); break;
case ArmInstruction.STREX: RewriteStrex(); break;
case ArmInstruction.SUB: RewriteBinop((a, b) => m.ISub(a, b)); break;
case ArmInstruction.SUBW: RewriteSubw(); break;
case ArmInstruction.TRAP: RewriteTrap(); break;
case ArmInstruction.TST: RewriteTst(); break;
case ArmInstruction.UDF: RewriteUdf(); break;
case ArmInstruction.UXTH: RewriteUxth(); break;
}
itState = (itState << 1) & 0x0F;
if (itState == 0)
{
itStateCondition = ArmCodeCondition.AL;
}
yield return(new RtlInstructionCluster(
instrs.Current.Address,
instr.Bytes.Length,
rtlInstructions.ToArray())
{
Class = rtlc
});
}
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
var addr = dasm.Current.Address;
var len = dasm.Current.Length;
rtlInstructions = new List <RtlInstruction>();
rtlc = RtlClass.Linear;
m = new RtlEmitter(rtlInstructions);
this.instr = dasm.Current;
switch (instr.Opcode)
{
default:
throw new AddressCorrelatedException(
instr.Address,
"Rewriting of Xtensa instruction '{0}' not implemented yet.",
instr.Opcode);
case Opcodes.abs: RewritePseudoFn("abs"); break;
case Opcodes.add:
case Opcodes.add_n: RewriteBinOp(m.IAdd); break;
case Opcodes.add_s: RewriteBinOp(m.FAdd); break;
case Opcodes.addi: RewriteAddi(); break;
case Opcodes.addi_n: RewriteAddi(); break;
case Opcodes.addmi: RewriteBinOp(m.IAdd); break;
case Opcodes.addx2: RewriteAddx(2); break;
case Opcodes.addx4: RewriteAddx(4); break;
case Opcodes.addx8: RewriteAddx(8); break;
case Opcodes.and: RewriteBinOp(m.And); break;
case Opcodes.andbc: RewriteBinOp((a, b) => m.And(a, m.Not(b))); break;
case Opcodes.ball: RewriteBall(); break;
case Opcodes.bany: RewriteBany(); break;
case Opcodes.bbc:
case Opcodes.bbci: RewriteBbx(m.Eq0); break;
case Opcodes.bbs:
case Opcodes.bbsi: RewriteBbx(m.Ne0); break;
case Opcodes.beq:
case Opcodes.beqi: RewriteBranch(m.Eq); break;
case Opcodes.beqz:
case Opcodes.beqz_n: RewriteBranchZ(m.Eq0); break;
case Opcodes.bge:
case Opcodes.bgei: RewriteBranch(m.Ge); break;
case Opcodes.bgeu:
case Opcodes.bgeui: RewriteBranch(m.Uge); break;
case Opcodes.bgez: RewriteBranchZ(m.Ge0); break;
case Opcodes.blt: RewriteBranch(m.Lt); break;
case Opcodes.blti: RewriteBranch(m.Lt); break;
case Opcodes.bltu:
case Opcodes.bltui: RewriteBranch(m.Ult); break;
case Opcodes.bltz: RewriteBranchZ(m.Lt0); break;
case Opcodes.bnall: RewriteBnall(); break;
case Opcodes.bne: RewriteBranch(m.Ne); break;
case Opcodes.bnei: RewriteBranch(m.Ne); break;
case Opcodes.bnez:
case Opcodes.bnez_n: RewriteBranchZ(m.Ne0); break;
case Opcodes.bnone: RewriteBnone(); break;
case Opcodes.@break: RewriteBreak(); break;
case Opcodes.call0:
case Opcodes.callx0: RewriteCall0(); break;
case Opcodes.extui: RewriteExtui(); break;
case Opcodes.floor_s: RewritePseudoFn("__floor"); break;
case Opcodes.isync: RewritePseudoProc("__isync"); break;
case Opcodes.j:
case Opcodes.jx: RewriteJ(); break;
case Opcodes.ill: RewriteIll(); break;
case Opcodes.l16si: RewriteLsi(PrimitiveType.Int16); break;
case Opcodes.l16ui: RewriteLui(PrimitiveType.UInt16); break;
case Opcodes.l32i: RewriteL32i(); break;
case Opcodes.l32e: RewriteL32e(); break;
case Opcodes.l32i_n: RewriteL32i(); break;
case Opcodes.l32r: RewriteCopy(); break;
case Opcodes.l8ui: RewriteLui(PrimitiveType.Byte); break;
case Opcodes.ldpte: RewritePseudoProc("__ldpte"); break;
case Opcodes.lsiu: RewriteLsiu(); break;
case Opcodes.memw: RewriteNop(); break; /// memory sync barriers?
case Opcodes.mov_n: RewriteCopy(); break;
case Opcodes.movi: RewriteCopy(); break;
case Opcodes.movi_n: RewriteMovi_n(); break;
case Opcodes.moveqz:
case Opcodes.moveqz_s: RewriteMovcc(m.Eq); break;
case Opcodes.movltz: RewriteMovcc(m.Lt); break;
case Opcodes.movgez: RewriteMovcc(m.Ge); break;
case Opcodes.movnez: RewriteMovcc(m.Ne); break;
case Opcodes.mul_s: RewriteBinOp(m.FMul); break;
case Opcodes.mul16s: RewriteMul16(m.SMul, Domain.SignedInt); break;
case Opcodes.mul16u: RewriteMul16(m.UMul, Domain.UnsignedInt); break;
case Opcodes.mull: RewriteBinOp(m.IMul); break;
case Opcodes.neg: RewriteUnaryOp(m.Neg); break;
case Opcodes.nsa: RewritePseudoFn("__nsa"); break;
case Opcodes.nsau: RewritePseudoFn("__nsau"); break;
case Opcodes.or: RewriteOr(); break;
case Opcodes.orbc: RewriteBinOp((a, b) => m.Or(a, m.Not(b))); break;
case Opcodes.quos: RewriteBinOp(m.SDiv); break;
case Opcodes.quou: RewriteBinOp(m.UDiv); break;
case Opcodes.rems: RewriteBinOp(m.Mod); break;
case Opcodes.remu: RewriteBinOp(m.Mod); break;
case Opcodes.reserved: RewriteReserved(); break;
case Opcodes.ret:
case Opcodes.ret_n: RewriteRet(); break;
case Opcodes.rfe: RewriteRet(); break; //$REVIEW: emit some hint this is a return from exception?
case Opcodes.rfi: RewriteRet(); break; //$REVIEW: emit some hint this is a return from interrupt?
case Opcodes.rsil: RewritePseudoFn("__rsil"); break;
case Opcodes.rsr: RewriteCopy(); break;
case Opcodes.s16i: RewriteSi(PrimitiveType.Word16); break;
case Opcodes.s32e: RewriteS32e(); break;
case Opcodes.s32i:
case Opcodes.s32i_n: RewriteSi(PrimitiveType.Word32); break;
case Opcodes.s32ri: RewriteSi(PrimitiveType.Word32); break; //$REVIEW: what about concurrency semantics
case Opcodes.s8i: RewriteSi(PrimitiveType.Byte); break;
case Opcodes.sll: RewriteShift(m.Shl); break;
case Opcodes.slli: RewriteShiftI(m.Shl); break;
case Opcodes.sra: RewriteShift(m.Sar); break;
case Opcodes.srai: RewriteShiftI(m.Sar); break;
case Opcodes.src: RewriteSrc(); break;
case Opcodes.srl: RewriteShift(m.Sar); break;
case Opcodes.srli: RewriteShiftI(m.Shr); break;
case Opcodes.ssa8l: RewriteSsa8l(); break;
case Opcodes.ssi: RewriteSi(PrimitiveType.Real32); break;
case Opcodes.ssl: RewriteSsl(); break;
case Opcodes.ssr:
case Opcodes.ssai: RewriteSsa(); break;
case Opcodes.sub: RewriteBinOp(m.ISub); break;
case Opcodes.sub_s: RewriteBinOp(m.FSub); break;
case Opcodes.subx2: RewriteSubx(2); break;
case Opcodes.subx4: RewriteSubx(4); break;
case Opcodes.subx8: RewriteSubx(8); break;
case Opcodes.ueq_s: RewriteBinOp(m.Eq); break;
case Opcodes.wsr: RewriteWsr(); break;
case Opcodes.xor: RewriteBinOp(m.Xor); break;
}
yield return(new RtlInstructionCluster(addr, len, rtlInstructions.ToArray())
{
Class = rtlc,
});
}
}
/// <summary>
/// Generates an RtlGoto instruction.
/// </summary>
/// <param name="target">Destination of the goto</param>
/// <param name="rtlClass">Details of the goto instruction</param>
/// <returns>A reference to this RtlEmitter.</returns>
public RtlEmitter Goto(Expression target, RtlClass rtlClass)
{
instrs.Add(new RtlGoto(target, rtlClass));
return(this);
}
private void RewriteUnary(Func <Expression, Expression> fn)
{
rtlc = RtlClass.Linear;
var src = SrcOp(instr.op1);
var dst = DstOp(instr.op2, src, fn);
}
private void RewriteFldi(float f)
{
rtlc = RtlClass.Linear;
DstOp(instr.op1, Constant.Real32(f), a => a);
}
private void RewriteRts()
{
rtlc = RtlClass.Transfer | RtlClass.Delay;
m.Return(0, 0);
}
private void RewriteShift(Func <Expression, Expression, Expression> fn, int c)
{
rtlc = RtlClass.Linear;
var src = Constant.Int32(c);
var dst = DstOp(instr.op1, src, fn);
}
private void RewriteMovt()
{
rtlc = RtlClass.Linear;
var t = binder.EnsureFlagGroup(Registers.T);
var dst = DstOp(instr.op1, t, a => m.Cast(PrimitiveType.Int32, a));
}
private void RewriteMova()
{
rtlc = RtlClass.Linear;
var src = (MemoryAccess)SrcOp(instr.op1, a => (sbyte)a);
var dst = DstOp(instr.op2, src.EffectiveAddress, a => a);
}
private void RewriteMov()
{
rtlc = RtlClass.Linear;
var src = SrcOp(instr.op1, a => (sbyte)a);
var dst = DstOp(instr.op2, src, a => a);
}
public RtlEmitter Goto(Expression target, RtlClass rtlClass)
{
instrs.Add(new RtlGoto(target, rtlClass));
return this;
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (instrs.MoveNext())
{
if (!instrs.Current.TryGetInternal(out this.instr))
{
throw new AddressCorrelatedException(
instrs.Current.Address,
"Invalid opcode cannot be rewritten to IR.");
}
this.ops = instr.ArchitectureDetail.Operands;
this.rtlInstructions = new List <RtlInstruction>();
this.rtlc = RtlClass.Linear;
this.m = new RtlEmitter(rtlInstructions);
switch (instr.Id)
{
default:
case Opcode.ADR:
case Opcode.AESD:
case Opcode.AESE:
case Opcode.AESIMC:
case Opcode.AESMC:
case Opcode.BKPT:
case Opcode.BXJ:
case Opcode.CDP:
case Opcode.CDP2:
case Opcode.CLREX:
case Opcode.CRC32B:
case Opcode.CRC32CB:
case Opcode.CRC32CH:
case Opcode.CRC32CW:
case Opcode.CRC32H:
case Opcode.CRC32W:
case Opcode.DBG:
case Opcode.DSB:
case Opcode.FLDMDBX:
case Opcode.FLDMIAX:
case Opcode.VMRS:
case Opcode.FSTMDBX:
case Opcode.FSTMIAX:
case Opcode.HINT:
case Opcode.HLT:
case Opcode.ISB:
case Opcode.LDA:
case Opcode.LDAB:
case Opcode.LDAEX:
case Opcode.LDAEXB:
case Opcode.LDAEXD:
case Opcode.LDAEXH:
case Opcode.LDAH:
case Opcode.LDC2L:
case Opcode.LDC2:
case Opcode.LDCL:
case Opcode.LDC:
case Opcode.LDMDA:
case Opcode.LDRBT:
case Opcode.LDREX:
case Opcode.LDREXB:
case Opcode.LDREXD:
case Opcode.LDREXH:
case Opcode.LDRHT:
case Opcode.LDRSBT:
case Opcode.LDRSHT:
case Opcode.LDRT:
case Opcode.MCR2:
case Opcode.MCRR:
case Opcode.MCRR2:
case Opcode.MRC2:
case Opcode.MRRC:
case Opcode.MRRC2:
case Opcode.PKHBT:
case Opcode.PKHTB:
case Opcode.PLDW:
case Opcode.PLD:
case Opcode.PLI:
case Opcode.QADD:
case Opcode.QADD16:
case Opcode.QADD8:
case Opcode.QASX:
case Opcode.QDADD:
case Opcode.QDSUB:
case Opcode.QSAX:
case Opcode.QSUB:
case Opcode.QSUB16:
case Opcode.QSUB8:
case Opcode.RBIT:
case Opcode.REV16:
case Opcode.REVSH:
case Opcode.RFEDA:
case Opcode.RFEDB:
case Opcode.RFEIA:
case Opcode.RFEIB:
case Opcode.RSC:
case Opcode.SADD16:
case Opcode.SADD8:
case Opcode.SASX:
case Opcode.SDIV:
case Opcode.SEL:
case Opcode.SETEND:
case Opcode.SHA1C:
case Opcode.SHA1H:
case Opcode.SHA1M:
case Opcode.SHA1P:
case Opcode.SHA1SU0:
case Opcode.SHA1SU1:
case Opcode.SHA256H:
case Opcode.SHA256H2:
case Opcode.SHA256SU0:
case Opcode.SHA256SU1:
case Opcode.SHADD16:
case Opcode.SHADD8:
case Opcode.SHASX:
case Opcode.SHSAX:
case Opcode.SHSUB16:
case Opcode.SHSUB8:
case Opcode.SMC:
case Opcode.SMLABB:
case Opcode.SMLABT:
case Opcode.SMLAD:
case Opcode.SMLADX:
case Opcode.SMLAL:
case Opcode.SMLALBB:
case Opcode.SMLALBT:
case Opcode.SMLALD:
case Opcode.SMLALDX:
case Opcode.SMLALTB:
case Opcode.SMLALTT:
case Opcode.SMLATB:
case Opcode.SMLATT:
case Opcode.SMLAWB:
case Opcode.SMLAWT:
case Opcode.SMLSD:
case Opcode.SMLSDX:
case Opcode.SMLSLD:
case Opcode.SMLSLDX:
case Opcode.SMMLA:
case Opcode.SMMLAR:
case Opcode.SMMLS:
case Opcode.SMMLSR:
case Opcode.SMMUL:
case Opcode.SMMULR:
case Opcode.SMUAD:
case Opcode.SMUADX:
case Opcode.SMULBT:
case Opcode.SMULTB:
case Opcode.SMULTT:
case Opcode.SMULWB:
case Opcode.SMULWT:
case Opcode.SMUSD:
case Opcode.SMUSDX:
case Opcode.SRSDA:
case Opcode.SRSDB:
case Opcode.SRSIA:
case Opcode.SRSIB:
case Opcode.SSAT:
case Opcode.SSAT16:
case Opcode.SSAX:
case Opcode.SSUB16:
case Opcode.SSUB8:
case Opcode.STC2L:
case Opcode.STC2:
case Opcode.STCL:
case Opcode.STC:
case Opcode.STL:
case Opcode.STLB:
case Opcode.STLEX:
case Opcode.STLEXB:
case Opcode.STLEXD:
case Opcode.STLEXH:
case Opcode.STLH:
case Opcode.STMDA:
case Opcode.STRBT:
case Opcode.STREX:
case Opcode.STREXB:
case Opcode.STREXD:
case Opcode.STREXH:
case Opcode.STRHT:
case Opcode.STRT:
case Opcode.SWP:
case Opcode.SWPB:
case Opcode.SXTAB16:
case Opcode.SXTB16:
case Opcode.TRAP:
case Opcode.UADD16:
case Opcode.UADD8:
case Opcode.UASX:
case Opcode.UDF:
case Opcode.UDIV:
case Opcode.UHADD16:
case Opcode.UHADD8:
case Opcode.UHASX:
case Opcode.UHSAX:
case Opcode.UHSUB16:
case Opcode.UHSUB8:
case Opcode.UMAAL:
case Opcode.UQADD16:
case Opcode.UQADD8:
case Opcode.UQASX:
case Opcode.UQSAX:
case Opcode.UQSUB16:
case Opcode.UQSUB8:
case Opcode.USAD8:
case Opcode.USADA8:
case Opcode.USAT:
case Opcode.USAT16:
case Opcode.USAX:
case Opcode.USUB16:
case Opcode.USUB8:
case Opcode.UXTAB16:
case Opcode.UXTB16:
case Opcode.VABAL:
case Opcode.VABA:
case Opcode.VABDL:
case Opcode.VABD:
case Opcode.VABS:
case Opcode.VACGE:
case Opcode.VACGT:
case Opcode.VADD:
case Opcode.VADDHN:
case Opcode.VADDL:
case Opcode.VADDW:
case Opcode.VAND:
case Opcode.VBIC:
case Opcode.VBIF:
case Opcode.VBIT:
case Opcode.VBSL:
case Opcode.VCEQ:
case Opcode.VCGE:
case Opcode.VCGT:
case Opcode.VCLE:
case Opcode.VCLS:
case Opcode.VCLT:
case Opcode.VCLZ:
case Opcode.VCMP:
case Opcode.VCMPE:
case Opcode.VCNT:
case Opcode.VCVTA:
case Opcode.VCVTB:
case Opcode.VCVT:
case Opcode.VCVTM:
case Opcode.VCVTN:
case Opcode.VCVTP:
case Opcode.VCVTT:
case Opcode.VDIV:
case Opcode.VDUP:
case Opcode.VEOR:
case Opcode.VEXT:
case Opcode.VFMA:
case Opcode.VFMS:
case Opcode.VFNMA:
case Opcode.VFNMS:
case Opcode.VHADD:
case Opcode.VHSUB:
case Opcode.VLD1:
case Opcode.VLD2:
case Opcode.VLD3:
case Opcode.VLD4:
case Opcode.VLDMDB:
case Opcode.VLDR:
case Opcode.VMAXNM:
case Opcode.VMAX:
case Opcode.VMINNM:
case Opcode.VMIN:
case Opcode.VMLA:
case Opcode.VMLAL:
case Opcode.VMLS:
case Opcode.VMLSL:
case Opcode.VMOVL:
case Opcode.VMOVN:
case Opcode.VMSR:
case Opcode.VMUL:
case Opcode.VMULL:
case Opcode.VMVN:
case Opcode.VNEG:
case Opcode.VNMLA:
case Opcode.VNMLS:
case Opcode.VNMUL:
case Opcode.VORN:
case Opcode.VORR:
case Opcode.VPADAL:
case Opcode.VPADDL:
case Opcode.VPADD:
case Opcode.VPMAX:
case Opcode.VPMIN:
case Opcode.VQABS:
case Opcode.VQADD:
case Opcode.VQDMLAL:
case Opcode.VQDMLSL:
case Opcode.VQDMULH:
case Opcode.VQDMULL:
case Opcode.VQMOVUN:
case Opcode.VQMOVN:
case Opcode.VQNEG:
case Opcode.VQRDMULH:
case Opcode.VQRSHL:
case Opcode.VQRSHRN:
case Opcode.VQRSHRUN:
case Opcode.VQSHL:
case Opcode.VQSHLU:
case Opcode.VQSHRN:
case Opcode.VQSHRUN:
case Opcode.VQSUB:
case Opcode.VRADDHN:
case Opcode.VRECPE:
case Opcode.VRECPS:
case Opcode.VREV16:
case Opcode.VREV32:
case Opcode.VREV64:
case Opcode.VRHADD:
case Opcode.VRINTA:
case Opcode.VRINTM:
case Opcode.VRINTN:
case Opcode.VRINTP:
case Opcode.VRINTR:
case Opcode.VRINTX:
case Opcode.VRINTZ:
case Opcode.VRSHL:
case Opcode.VRSHRN:
case Opcode.VRSHR:
case Opcode.VRSQRTE:
case Opcode.VRSQRTS:
case Opcode.VRSRA:
case Opcode.VRSUBHN:
case Opcode.VSELEQ:
case Opcode.VSELGE:
case Opcode.VSELGT:
case Opcode.VSELVS:
case Opcode.VSHLL:
case Opcode.VSHL:
case Opcode.VSHRN:
case Opcode.VSHR:
case Opcode.VSLI:
case Opcode.VSQRT:
case Opcode.VSRA:
case Opcode.VSRI:
case Opcode.VST1:
case Opcode.VST2:
case Opcode.VST3:
case Opcode.VST4:
case Opcode.VSTMDB:
case Opcode.VSTR:
case Opcode.VSUB:
case Opcode.VSUBHN:
case Opcode.VSUBL:
case Opcode.VSUBW:
case Opcode.VSWP:
case Opcode.VTBL:
case Opcode.VTBX:
case Opcode.VCVTR:
case Opcode.VTRN:
case Opcode.VTST:
case Opcode.VUZP:
case Opcode.VZIP:
case Opcode.ADDW:
case Opcode.ASR:
case Opcode.DCPS1:
case Opcode.DCPS2:
case Opcode.DCPS3:
case Opcode.IT:
case Opcode.LSL:
case Opcode.LSR:
case Opcode.ASRS:
case Opcode.LSRS:
case Opcode.ORN:
case Opcode.ROR:
case Opcode.RRX:
case Opcode.SUBS:
case Opcode.SUBW:
case Opcode.TBB:
case Opcode.TBH:
case Opcode.CBNZ:
case Opcode.CBZ:
case Opcode.MOVS:
case Opcode.YIELD:
case Opcode.WFE:
case Opcode.WFI:
case Opcode.SEV:
case Opcode.SEVL:
case Opcode.VPUSH:
case Opcode.VPOP:
NotImplementedYet();
break;
case Opcode.ADC: RewriteAdcSbc(m.IAdd); break;
case Opcode.ADD: RewriteBinOp(m.IAdd, instr.ArchitectureDetail.UpdateFlags); break;
case Opcode.AND: RewriteBinOp(m.And, instr.ArchitectureDetail.UpdateFlags); break;
case Opcode.EOR: RewriteBinOp(m.Xor, instr.ArchitectureDetail.UpdateFlags); break;
case Opcode.B: RewriteB(false); break;
case Opcode.BFC: RewriteBfc(); break;
case Opcode.BFI: RewriteBfi(); break;
case Opcode.BIC: RewriteBic(); break;
case Opcode.BL: RewriteB(true); break;
case Opcode.BLX: RewriteB(true); break;
case Opcode.BX: RewriteB(false); break;
case Opcode.CLZ: RewriteClz(); break;
case Opcode.CMN: RewriteCmn(); break;
case Opcode.CMP: RewriteCmp(); break;
case Opcode.CPS: RewriteCps(); break;
case Opcode.DMB: RewriteDmb(); break;
case Opcode.LDR: RewriteLdr(PrimitiveType.Word32); break;
case Opcode.LDRB: RewriteLdr(PrimitiveType.Byte); break;
case Opcode.LDRH: RewriteLdr(PrimitiveType.UInt16); break;
case Opcode.LDRSB: RewriteLdr(PrimitiveType.SByte); break;
case Opcode.LDRSH: RewriteLdr(PrimitiveType.Int16); break;
case Opcode.LDRD: RewriteLdrd(); break;
case Opcode.LDM: RewriteLdm(0); break;
case Opcode.LDMDB: RewriteLdm(0); break;
case Opcode.LDMIB: RewriteLdm(4); break;
case Opcode.NOP: m.Nop(); break;
case Opcode.MCR: RewriteMcr(); break;
case Opcode.MLA: RewriteMultiplyAccumulate(m.IAdd); break;
case Opcode.MLS: RewriteMultiplyAccumulate(m.ISub); break;
case Opcode.MOV: RewriteMov(); break;
case Opcode.MOVT: RewriteMovt(); break;
case Opcode.MOVW: RewriteMov(); break;
case Opcode.MRC: RewriteMrc(); break;
case Opcode.MRS: RewriteMrs(); break;
case Opcode.MSR: RewriteMsr(); break;
case Opcode.MUL: RewriteBinOp(m.IMul, instr.ArchitectureDetail.UpdateFlags); break;
case Opcode.MVN: RewriteUnaryOp(Operator.Not); break;
case Opcode.ORR: RewriteBinOp(m.Or, false); break;
case Opcode.POP: RewritePop(); break;
case Opcode.PUSH: RewritePush(); break;
case Opcode.REV: RewriteRev(); break;
case Opcode.RSB: RewriteRevBinOp(Operator.ISub, instr.ArchitectureDetail.UpdateFlags); break;
case Opcode.SBC: RewriteAdcSbc(m.ISub); break;
case Opcode.SBFX: RewriteSbfx(); break;
case Opcode.SMULBB: RewriteMulbb(false, false, PrimitiveType.Int16, m.SMul); break;
case Opcode.SMULL: RewriteMull(PrimitiveType.Int64, m.SMul); break;
case Opcode.STM: RewriteStm(); break;
case Opcode.STMDB: RewriteStm(); break;
case Opcode.STMIB: RewriteStmib(); break;
case Opcode.STR: RewriteStr(PrimitiveType.Word32); break;
case Opcode.STRB: RewriteStr(PrimitiveType.Byte); break;
case Opcode.STRD: RewriteStrd(); break;
case Opcode.STRH: RewriteStr(PrimitiveType.UInt16); break;
case Opcode.SUB: RewriteBinOp(m.ISub, instr.ArchitectureDetail.UpdateFlags); break;
case Opcode.SVC: RewriteSvc(); break;
case Opcode.SXTAB: RewriteXtab(PrimitiveType.SByte); break;
case Opcode.SXTAH: RewriteXtab(PrimitiveType.Int16); break;
case Opcode.SXTB: RewriteXtb(PrimitiveType.SByte); break;
case Opcode.SXTH: RewriteXtb(PrimitiveType.Int16); break;
case Opcode.TEQ: RewriteTeq(); break;
case Opcode.TST: RewriteTst(); break;
case Opcode.UBFX: RewriteUbfx(); break;
case Opcode.UMLAL: RewriteUmlal(); break;
case Opcode.UMULL: RewriteMull(PrimitiveType.UInt64, m.UMul); break;
case Opcode.UXTAB: RewriteXtab(PrimitiveType.Byte); break;
case Opcode.UXTAH: RewriteXtab(PrimitiveType.UInt16); break;
case Opcode.UXTB: RewriteXtb(PrimitiveType.Byte); break;
case Opcode.UXTH: RewriteXtb(PrimitiveType.UInt16); break;
case Opcode.VLDMIA: RewriteVldmia(); break;
case Opcode.VMOV: RewriteVmov(); break;
case Opcode.VSTMIA: RewriteVstmia(); break;
}
yield return(new RtlInstructionCluster(
instrs.Current.Address,
instr.Bytes.Length,
rtlInstructions.ToArray())
{
Class = rtlc
});
}
instrs.Dispose();
}
/// <summary>
/// Called when we need to generate an RtlBranch in the middle of an operation.
/// Normally, branches are at the end of the Rtl's of a translated instruction,
/// but in some cases, they are not.
/// </summary>
/// <param name="condition"></param>
/// <param name="target"></param>
/// <param name="?"></param>
public void BranchInMiddleOfInstruction(Expression condition, Address target, RtlClass rtlClass)
{
var branch = new RtlBranch(condition, target, rtlClass);
branch.NextStatementRequiresLabel = true;
instrs.Add(branch);
}
public RtlInstruction Branch(Expression cond, Address target, RtlClass rtlClass)
{
var br = new RtlBranch(cond, target, rtlClass);
return(Emit(br));
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
var addr = dasm.Current.Address;
var len = dasm.Current.Length;
rtlInstructions = new List <RtlInstruction>();
rtlc = RtlClass.Linear;
m = new RtlEmitter(rtlInstructions);
switch (dasm.Current.Opcode)
{
default:
//EmitUnitTest();
//emitter.SideEffect(Constant.String(
// dasm.Current.ToString(),
// StringType.NullTerminated(PrimitiveType.Char)));
host.Warn(
dasm.Current.Address,
"VAX instruction {0} not supported yet.",
dasm.Current.Opcode);
m.Invalid();
break;
case Opcode.Invalid: m.Invalid(); break;
case Opcode.Reserved: m.Invalid(); break;
case Opcode.acbb: RewriteAcbi(PrimitiveType.Byte); break;
case Opcode.acbd: RewriteAcbf(PrimitiveType.Real64); break;
case Opcode.acbf: RewriteAcbf(PrimitiveType.Real32); break;
case Opcode.acbg: RewriteAcbf(PrimitiveType.Real64); break;
case Opcode.acbh: RewriteAcbf(PrimitiveType.Real128); break;
case Opcode.acbl: RewriteAcbi(PrimitiveType.Word32); break;
case Opcode.acbw: RewriteAcbi(PrimitiveType.Word16); break;
case Opcode.adawi: RewriteAlu2(PrimitiveType.Word16, Adawi, AllFlags); break;
case Opcode.addb2: RewriteAlu2(PrimitiveType.Byte, m.IAdd, AllFlags); break;
case Opcode.addb3: RewriteAlu3(PrimitiveType.Byte, m.IAdd, AllFlags); break;
case Opcode.addd2: RewriteFpu2(PrimitiveType.Real64, m.FAdd, NZ00); break;
case Opcode.addd3: RewriteFpu3(PrimitiveType.Real64, m.FAdd, NZ00); break;
case Opcode.addf2: RewriteFpu2(PrimitiveType.Real32, m.FAdd, NZ00); break;
case Opcode.addf3: RewriteFpu3(PrimitiveType.Real32, m.FAdd, NZ00); break;
case Opcode.addl2: RewriteAlu2(PrimitiveType.Word32, m.IAdd, AllFlags); break;
case Opcode.addl3: RewriteAlu3(PrimitiveType.Word32, m.IAdd, AllFlags); break;
case Opcode.addp4: RewriteP4("vax_addp4"); break;
case Opcode.addp6: RewriteP6("vax_addp6"); break;
case Opcode.addw2: RewriteAlu2(PrimitiveType.Word16, m.IAdd, AllFlags); break;
case Opcode.addw3: RewriteAlu3(PrimitiveType.Word16, m.IAdd, AllFlags); break;
case Opcode.adwc: RewriteAdwc(); break;
case Opcode.aobleq: RewriteAob(m.Le); break;
case Opcode.aoblss: RewriteAob(m.Lt); break;
case Opcode.ashl: RewriteAsh(PrimitiveType.Word32); break;
case Opcode.ashp: RewriteAshp(); break;
case Opcode.ashq: RewriteAsh(PrimitiveType.Word64); break;
case Opcode.bbc: RewriteBb(false); break;
case Opcode.bbcc: RewriteBbxx(false, false); break;
case Opcode.bbcci: RewriteBbxxi(false); break;
case Opcode.bbcs: RewriteBbxx(false, true); break;
case Opcode.bbs: RewriteBb(true); break;
case Opcode.bbsc: RewriteBbxx(true, false); break;
case Opcode.bbss: RewriteBbxx(true, true); break;
case Opcode.bbssi: RewriteBbxxi(true); break;
case Opcode.beql: RewriteBranch(ConditionCode.EQ, FlagM.ZF); break;
case Opcode.bgeq: RewriteBranch(ConditionCode.GE, FlagM.NF); break;
case Opcode.bgequ: RewriteBranch(ConditionCode.UGE, FlagM.CF); break;
case Opcode.bgtr: RewriteBranch(ConditionCode.GT, FlagM.ZF | FlagM.NF); break;
case Opcode.bgtru: RewriteBranch(ConditionCode.UGT, FlagM.ZF | FlagM.CF); break;
case Opcode.bleq: RewriteBranch(ConditionCode.LE, FlagM.ZF | FlagM.NF); break;
case Opcode.blequ: RewriteBranch(ConditionCode.ULE, FlagM.ZF | FlagM.CF); break;
case Opcode.blss: RewriteBranch(ConditionCode.LT, FlagM.NF); break;
case Opcode.blssu: RewriteBranch(ConditionCode.ULT, FlagM.CF); break;
case Opcode.bneq: RewriteBranch(ConditionCode.NE, FlagM.ZF); break;
case Opcode.bvc: RewriteBranch(ConditionCode.NO, FlagM.VF); break;
case Opcode.bvs: RewriteBranch(ConditionCode.OV, FlagM.VF); break;
case Opcode.bicb2: RewriteAlu2(PrimitiveType.Byte, Bic, NZ00); break;
case Opcode.bicb3: RewriteAlu3(PrimitiveType.Byte, Bic, NZ00); break;
case Opcode.bicl2: RewriteAlu2(PrimitiveType.Word32, Bic, NZ00); break;
case Opcode.bicl3: RewriteAlu3(PrimitiveType.Word32, Bic, NZ00); break;
case Opcode.bicpsw: RewriteBicpsw(); break;
case Opcode.bicw2: RewriteAlu2(PrimitiveType.Word16, Bic, NZ00); break;
case Opcode.bicw3: RewriteAlu3(PrimitiveType.Word16, Bic, NZ00); break;
case Opcode.bisb2: RewriteAlu2(PrimitiveType.Byte, m.Or, NZ00); break;
case Opcode.bisb3: RewriteAlu3(PrimitiveType.Byte, m.Or, NZ00); break;
case Opcode.bispsw: RewriteBispsw(); break;
case Opcode.bisl2: RewriteAlu2(PrimitiveType.Word32, m.Or, NZ00); break;
case Opcode.bisl3: RewriteAlu3(PrimitiveType.Word32, m.Or, NZ00); break;
case Opcode.bisw2: RewriteAlu2(PrimitiveType.Word16, m.Or, NZ00); break;
case Opcode.bisw3: RewriteAlu3(PrimitiveType.Word16, m.Or, NZ00); break;
case Opcode.bitb: RewriteBit(PrimitiveType.Byte); break;
case Opcode.bitw: RewriteBit(PrimitiveType.Byte); break;
case Opcode.bitl: RewriteBit(PrimitiveType.Byte); break;
case Opcode.blbc: RewriteBlb(m.Eq0); break;
case Opcode.blbs: RewriteBlb(m.Ne0); break;
case Opcode.bpt: RewriteBpt(); break;
case Opcode.brb: RewriteBranch(); break;
case Opcode.brw: RewriteBranch(); break;
case Opcode.bsbb: RewriteBsb(); break;
case Opcode.bsbw: RewriteBsb(); break;
case Opcode.caseb: goto default;
case Opcode.casel: goto default;
case Opcode.chme: RewriteChm("vax_chme"); break;
case Opcode.chmk: RewriteChm("vax_chmk"); break;
case Opcode.chms: RewriteChm("vax_chms"); break;
case Opcode.chmu: RewriteChm("vax_chmu"); break;
case Opcode.clrb: RewriteClr(PrimitiveType.Byte); break;
case Opcode.clrh: RewriteClr(PrimitiveType.Word128); break;
case Opcode.clrl: RewriteClr(PrimitiveType.Word32); break;
case Opcode.clrq: RewriteClr(PrimitiveType.Word64); break;
case Opcode.clrw: RewriteClr(PrimitiveType.Word16); break;
case Opcode.cmpb: RewriteCmp(PrimitiveType.Byte); break;
case Opcode.cmpd: RewriteCmp(PrimitiveType.Real64); break;
case Opcode.cmpf: RewriteCmp(PrimitiveType.Real32); break;
case Opcode.cmpg: RewriteCmp(PrimitiveType.Real64); break;
case Opcode.cmph: RewriteCmp(PrimitiveType.Real128); break;
case Opcode.cmpl: RewriteCmp(PrimitiveType.Word32); break;
case Opcode.cmpw: RewriteCmp(PrimitiveType.Word16); break;
case Opcode.cmpp3: RewriteCmpp3(); break;
case Opcode.cmpp4: RewriteCmpp4(); break;
case Opcode.cmpv: goto default;
case Opcode.cmpzv: goto default;
case Opcode.cvtbd: RewriteCvt(PrimitiveType.SByte, PrimitiveType.Real64); break;
case Opcode.cvtbf: RewriteCvt(PrimitiveType.SByte, PrimitiveType.Real32); break;
case Opcode.cvtbg: RewriteCvt(PrimitiveType.SByte, PrimitiveType.Real64); break;
case Opcode.cvtbh: RewriteCvt(PrimitiveType.SByte, PrimitiveType.Real128); break;
case Opcode.cvtbl: RewriteCvt(PrimitiveType.SByte, PrimitiveType.Int32); break;
case Opcode.cvtbw: RewriteCvt(PrimitiveType.SByte, PrimitiveType.Int16); break;
case Opcode.cvtdb: RewriteCvt(PrimitiveType.Real64, PrimitiveType.SByte); break;
case Opcode.cvtdf: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Real32); break;
case Opcode.cvtdh: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Real128); break;
case Opcode.cvtdl: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Int32); break;
case Opcode.cvtdw: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Int16); break;
case Opcode.cvtfb: RewriteCvt(PrimitiveType.Real32, PrimitiveType.SByte); break;
case Opcode.cvtfd: RewriteCvt(PrimitiveType.Real32, PrimitiveType.Real64); break;
case Opcode.cvtfg: RewriteCvt(PrimitiveType.Real32, PrimitiveType.Real64); break;
case Opcode.cvtfh: RewriteCvt(PrimitiveType.Real32, PrimitiveType.Real128); break;
case Opcode.cvtfl: RewriteCvt(PrimitiveType.Real32, PrimitiveType.Int32); break;
case Opcode.cvtfw: RewriteCvt(PrimitiveType.Real32, PrimitiveType.Int16); break;
case Opcode.cvtgb: RewriteCvt(PrimitiveType.Real64, PrimitiveType.SByte); break;
case Opcode.cvtgf: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Real32); break;
case Opcode.cvtgh: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Real128); break;
case Opcode.cvtgl: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Int32); break;
case Opcode.cvtgw: RewriteCvt(PrimitiveType.Real64, PrimitiveType.Int16); break;
case Opcode.cvthb: RewriteCvt(PrimitiveType.Real128, PrimitiveType.SByte); break;
case Opcode.cvthd: RewriteCvt(PrimitiveType.Real128, PrimitiveType.Real64); break;
case Opcode.cvthf: RewriteCvt(PrimitiveType.Real128, PrimitiveType.Real32); break;
case Opcode.cvthg: RewriteCvt(PrimitiveType.Real128, PrimitiveType.Real64); break;
case Opcode.cvthl: RewriteCvt(PrimitiveType.Real128, PrimitiveType.Int32); break;
case Opcode.cvthw: RewriteCvt(PrimitiveType.Real128, PrimitiveType.Int16); break;
case Opcode.cvtps: RewriteCvtComplex("__cvtps"); break;
case Opcode.cvtrdl: RewriteCvtr(PrimitiveType.Real64, PrimitiveType.Int32); break;
case Opcode.cvtrfl: RewriteCvtr(PrimitiveType.Real32, PrimitiveType.Int32); break;
case Opcode.cvtrgl: RewriteCvtr(PrimitiveType.Real64, PrimitiveType.Int32); break;
case Opcode.cvtrhl: RewriteCvtr(PrimitiveType.Real128, PrimitiveType.Int32); break;
case Opcode.cvtlb: RewriteCvt(PrimitiveType.Int32, PrimitiveType.SByte); break;
case Opcode.cvtld: RewriteCvt(PrimitiveType.Int32, PrimitiveType.Real64); break;
case Opcode.cvtlf: RewriteCvt(PrimitiveType.Int32, PrimitiveType.Real32); break;
case Opcode.cvtlg: RewriteCvt(PrimitiveType.Int32, PrimitiveType.Real64); break;
case Opcode.cvtlh: RewriteCvt(PrimitiveType.Int32, PrimitiveType.Real128); break;
case Opcode.cvtlp: goto default;
case Opcode.cvtlw: RewriteCvt(PrimitiveType.Int32, PrimitiveType.Int16); break;
case Opcode.cvtpl: goto default;
case Opcode.cvtpt: goto default;
case Opcode.cvtsp: RewriteCvtComplex("__cvtsp"); break;
case Opcode.cvttp: goto default;
case Opcode.cvtwb: RewriteCvt(PrimitiveType.Int16, PrimitiveType.SByte); break;
case Opcode.cvtwd: RewriteCvt(PrimitiveType.Int16, PrimitiveType.Real64); break;
case Opcode.cvtwf: RewriteCvt(PrimitiveType.Int16, PrimitiveType.Real32); break;
case Opcode.cvtwg: RewriteCvt(PrimitiveType.Int16, PrimitiveType.Real64); break;
case Opcode.cvtwh: RewriteCvt(PrimitiveType.Int16, PrimitiveType.Real128); break;
case Opcode.cvtwl: RewriteCvt(PrimitiveType.Int16, PrimitiveType.Int32); break;;
case Opcode.decb: RewriteIncDec(PrimitiveType.Byte, Dec); break;
case Opcode.decl: RewriteIncDec(PrimitiveType.Word32, Dec); break;
case Opcode.decw: RewriteIncDec(PrimitiveType.Word16, Dec); break;
case Opcode.divb2: RewriteAlu2(PrimitiveType.Byte, m.SDiv, AllFlags); break;
case Opcode.divb3: RewriteAlu3(PrimitiveType.Byte, m.SDiv, AllFlags); break;
case Opcode.divd2: RewriteFpu2(PrimitiveType.Real64, m.FDiv, AllFlags); break;
case Opcode.divd3: RewriteFpu3(PrimitiveType.Real64, m.FDiv, AllFlags); break;
case Opcode.divf2: RewriteFpu2(PrimitiveType.Real32, m.FDiv, AllFlags); break;
case Opcode.divf3: RewriteFpu3(PrimitiveType.Real32, m.FDiv, AllFlags); break;
case Opcode.divl2: RewriteAlu2(PrimitiveType.Word32, m.SDiv, AllFlags); break;
case Opcode.divl3: RewriteAlu3(PrimitiveType.Word32, m.SDiv, AllFlags); break;
case Opcode.divp: RewriteDivp(); break;
case Opcode.divw2: RewriteAlu2(PrimitiveType.Word16, m.SDiv, AllFlags); break;
case Opcode.divw3: RewriteAlu3(PrimitiveType.Word16, m.SDiv, AllFlags); break;
case Opcode.emodd: RewriteEmod("emodd", PrimitiveType.Real64, PrimitiveType.Byte); break; //$TODO: VAX floating point types
case Opcode.emodf: RewriteEmod("emodf", PrimitiveType.Real32, PrimitiveType.Byte); break; //$TODO: VAX floating point types
case Opcode.emodg: RewriteEmod("emodg", PrimitiveType.Real64, PrimitiveType.Word16); break; //$TODO: VAX floating point types
case Opcode.emodh: RewriteEmod("emodh", PrimitiveType.Real128, PrimitiveType.Word16); break; //$TODO: VAX floating point types
case Opcode.ffc: RewriteFfx("__ffc"); break;
case Opcode.ffs: RewriteFfx("__ffs"); break;
case Opcode.halt: RewriteHalt(); break;
case Opcode.incb: RewriteIncDec(PrimitiveType.Byte, Inc); break;
case Opcode.incl: RewriteIncDec(PrimitiveType.Word32, Inc); break;
case Opcode.incw: RewriteIncDec(PrimitiveType.Word16, Inc); break;
case Opcode.insque: RewriteInsque(); break;
case Opcode.jmp: RewriteJmp(); break;
case Opcode.jsb: RewriteJsb(); break;
case Opcode.mcomb: RewriteAluUnary2(PrimitiveType.Byte, m.Comp, NZ00); break;
case Opcode.mcoml: RewriteAluUnary2(PrimitiveType.Word32, m.Comp, NZ00); break;
case Opcode.mcomw: RewriteAluUnary2(PrimitiveType.Word16, m.Comp, NZ00); break;
case Opcode.mnegb: RewriteAluUnary2(PrimitiveType.Byte, m.Neg, AllFlags); break;
case Opcode.mnegd: RewriteAluUnary2(PrimitiveType.Real64, m.FNeg, NZ00); break;
case Opcode.mnegf: RewriteAluUnary2(PrimitiveType.Real32, m.FNeg, NZ00); break;
case Opcode.mnegg: RewriteAluUnary2(PrimitiveType.Real64, m.FNeg, NZ00); break;
case Opcode.mnegh: RewriteAluUnary2(PrimitiveType.Word128, m.FNeg, NZ00); break;
case Opcode.mnegl: RewriteAluUnary2(PrimitiveType.Word32, m.Neg, AllFlags); break;
case Opcode.mnegw: RewriteAluUnary2(PrimitiveType.Word16, m.Neg, AllFlags); break;
case Opcode.movab: RewriteMova(PrimitiveType.Byte); break;
case Opcode.movah: RewriteMova(PrimitiveType.Real128); break;
case Opcode.moval: RewriteMova(PrimitiveType.Word32); break;
case Opcode.movaq: RewriteMova(PrimitiveType.Word64); break;
case Opcode.movaw: RewriteMova(PrimitiveType.Word16); break;
case Opcode.movb: RewriteAluUnary2(PrimitiveType.Byte, Copy, NZ00); break;
case Opcode.movc3: goto default;
case Opcode.movc5: goto default;
case Opcode.movd: RewriteAluUnary2(PrimitiveType.Real64, Copy, NZ00); break;
case Opcode.movf: RewriteAluUnary2(PrimitiveType.Real32, Copy, NZ00); break;
case Opcode.movg: RewriteAluUnary2(PrimitiveType.Real64, Copy, NZ00); break;
case Opcode.movh: RewriteAluUnary2(PrimitiveType.Real128, Copy, NZ00); break;
case Opcode.movl: RewriteAluUnary2(PrimitiveType.Word32, Copy, NZ00); break;
case Opcode.movo: RewriteAluUnary2(PrimitiveType.Word128, Copy, NZ00); break;
case Opcode.movp: goto default;
case Opcode.movq: RewriteAluUnary2(PrimitiveType.Word64, Copy, NZ00); break;
case Opcode.movw: RewriteAluUnary2(PrimitiveType.Word16, Copy, NZ00); break;
case Opcode.movzbl: RewriteMovz(PrimitiveType.Byte, PrimitiveType.UInt32); break;
case Opcode.movzbw: RewriteMovz(PrimitiveType.Byte, PrimitiveType.UInt16); break;
case Opcode.movzwl: RewriteMovz(PrimitiveType.Word16, PrimitiveType.UInt32); break;
case Opcode.mulb2: RewriteAlu2(PrimitiveType.Byte, m.IMul, AllFlags); break;
case Opcode.mulb3: RewriteAlu3(PrimitiveType.Byte, m.IMul, AllFlags); break;
case Opcode.muld2: RewriteAlu2(PrimitiveType.Real64, m.FMul, AllFlags); break;
case Opcode.muld3: RewriteAlu3(PrimitiveType.Real64, m.FMul, AllFlags); break;
case Opcode.mulf2: RewriteAlu2(PrimitiveType.Real32, m.FMul, AllFlags); break;
case Opcode.mulf3: RewriteAlu3(PrimitiveType.Real32, m.FMul, AllFlags); break;
case Opcode.mulg2: RewriteAlu2(PrimitiveType.Real64, m.FMul, AllFlags); break;
case Opcode.mulg3: RewriteAlu3(PrimitiveType.Real64, m.FMul, AllFlags); break;
case Opcode.mulh2: RewriteAlu2(PrimitiveType.Real128, m.FMul, AllFlags); break;
case Opcode.mulh3: RewriteAlu3(PrimitiveType.Real128, m.FMul, AllFlags); break;
case Opcode.mull2: RewriteAlu2(PrimitiveType.Word32, m.IMul, AllFlags); break;
case Opcode.mull3: RewriteAlu3(PrimitiveType.Word32, m.IMul, AllFlags); break;
case Opcode.mulp: RewriteMulp(); break;
case Opcode.mulw2: RewriteAlu2(PrimitiveType.Word16, m.IMul, AllFlags); break;
case Opcode.mulw3: RewriteAlu3(PrimitiveType.Word16, m.IMul, AllFlags); break;
case Opcode.nop: m.Nop(); break;
case Opcode.polyd: RewritePoly(PrimitiveType.Real64); break;
case Opcode.polyf: RewritePoly(PrimitiveType.Real32); break;
case Opcode.polyg: RewritePoly(PrimitiveType.Real64); break;
case Opcode.polyh: RewritePoly(PrimitiveType.Real128); break;
case Opcode.popr: goto default;
case Opcode.prober: goto default;
case Opcode.probew: goto default;
case Opcode.pushr: goto default;
case Opcode.pushab: RewritePusha(); break;
case Opcode.pushal: RewritePusha(); break;
case Opcode.pushah: RewritePusha(); break;
case Opcode.pushaw: RewritePusha(); break;
case Opcode.pushaq: RewritePusha(); break;
case Opcode.pushl: RewritePush(PrimitiveType.Word32); break;
case Opcode.rei: RewriteRei(); break;
case Opcode.ret: RewriteRet(); break;
case Opcode.rotl: RewriteAlu3(PrimitiveType.Word32, Rotl, NZ00); break;
case Opcode.rsb: RewriteRsb(); break;
case Opcode.sbwc: RewriteSbwc(); break;
case Opcode.scanc: RewriteScanc(); break;
case Opcode.sobgeq: RewriteSob(m.Ge); break;
case Opcode.sobgtr: RewriteSob(m.Gt); break;
case Opcode.subb2: RewriteAlu2(PrimitiveType.Byte, m.ISub, AllFlags); break;
case Opcode.subb3: RewriteAlu3(PrimitiveType.Byte, m.ISub, AllFlags); break;
case Opcode.subd2: RewriteAlu2(PrimitiveType.Real64, m.FSub, NZ00); break;
case Opcode.subd3: RewriteAlu3(PrimitiveType.Real64, m.FSub, NZ00); break;
case Opcode.subf2: RewriteAlu2(PrimitiveType.Real32, m.FSub, NZ00); break;
case Opcode.subf3: RewriteAlu3(PrimitiveType.Real32, m.FSub, NZ00); break;
case Opcode.subg2: RewriteAlu2(PrimitiveType.Real64, m.FSub, NZ00); break;
case Opcode.subg3: RewriteAlu3(PrimitiveType.Real64, m.FSub, NZ00); break;
case Opcode.subh2: RewriteAlu2(PrimitiveType.Real128, m.FSub, NZ00); break;
case Opcode.subh3: RewriteAlu3(PrimitiveType.Real128, m.FSub, NZ00); break;
case Opcode.subl2: RewriteAlu2(PrimitiveType.Word32, m.ISub, AllFlags); break;
case Opcode.subl3: RewriteAlu3(PrimitiveType.Word32, m.ISub, AllFlags); break;
case Opcode.subp4: RewriteP4("vax_subp4"); break;
case Opcode.subp6: RewriteP6("vax_subp6"); break;
case Opcode.subw2: RewriteAlu2(PrimitiveType.Word16, m.ISub, AllFlags); break;
case Opcode.subw3: RewriteAlu3(PrimitiveType.Word16, m.ISub, AllFlags); break;
case Opcode.tstb: RewriteTst(PrimitiveType.Byte, ICmp0); break;
case Opcode.tstd: RewriteTst(PrimitiveType.Real64, FCmp0); break;
case Opcode.tstf: RewriteTst(PrimitiveType.Real32, FCmp0); break;
case Opcode.tstg: RewriteTst(PrimitiveType.Real64, FCmp0); break;
case Opcode.tsth: RewriteTst(PrimitiveType.Real128, FCmp0); break;
case Opcode.tstl: RewriteTst(PrimitiveType.Word32, ICmp0); break;
case Opcode.tstw: RewriteTst(PrimitiveType.Word16, ICmp0); break;
case Opcode.xorb2: RewriteAlu2(PrimitiveType.Byte, m.Xor, NZ00); break;
case Opcode.xorb3: RewriteAlu3(PrimitiveType.Byte, m.Xor, NZ00); break;
case Opcode.xorl2: RewriteAlu2(PrimitiveType.Word32, m.Xor, NZ00); break;
case Opcode.xorl3: RewriteAlu3(PrimitiveType.Word32, m.Xor, NZ00); break;
case Opcode.xorw2: RewriteAlu2(PrimitiveType.Word16, m.Xor, NZ00); break;
case Opcode.xorw3: RewriteAlu3(PrimitiveType.Word16, m.Xor, NZ00); break;
case Opcode.ldpctx: goto default;
case Opcode.svpctx: goto default;
case Opcode.editpc: goto default;
case Opcode.matchc: goto default;
case Opcode.index: goto default;
case Opcode.locc: goto default;
case Opcode.crc: goto default;
case Opcode.skpc: goto default;
case Opcode.remque: goto default;
case Opcode.spanc: goto default;
case Opcode.insqhi: goto default;
case Opcode.insqti: goto default;
case Opcode.movtc: goto default;
case Opcode.remqhi: goto default;
case Opcode.movtuc: goto default;
case Opcode.remqti: goto default;
case Opcode.emul: goto default;
case Opcode.ediv: goto default;
case Opcode.casew: goto default;
case Opcode.extv: goto default;
case Opcode.extzv: goto default;
case Opcode.insv: goto default;
case Opcode.mtpr: goto default;
case Opcode.callg: goto default;
case Opcode.mfpr: goto default;
case Opcode.calls: goto default;
case Opcode.movpsl: goto default;
case Opcode.xfc: goto default;
case Opcode.mfvp: goto default;
case Opcode.vldl: goto default;
case Opcode.vgathl: goto default;
case Opcode.vldq: goto default;
case Opcode.vgathq: goto default;
case Opcode.addg2: goto default;
case Opcode.addg3: goto default;
case Opcode.divg2: goto default;
case Opcode.divg3: goto default;
case Opcode.addh2: goto default;
case Opcode.addh3: goto default;
case Opcode.divh2: goto default;
case Opcode.divh3: goto default;
case Opcode.vstl: goto default;
case Opcode.vscatl: goto default;
case Opcode.vstq: goto default;
case Opcode.vscatq: goto default;
case Opcode.vvmull: goto default;
case Opcode.vsmull: goto default;
case Opcode.vvmulg: goto default;
case Opcode.vsmulg: goto default;
case Opcode.vvmulf: goto default;
case Opcode.vsmulf: goto default;
case Opcode.vvmuld: goto default;
case Opcode.vsmuld: goto default;
case Opcode.vsync: goto default;
case Opcode.mtvp: goto default;
case Opcode.vvdivg: goto default;
case Opcode.vsdivg: goto default;
case Opcode.vvdivf: goto default;
case Opcode.vsdivf: goto default;
case Opcode.vvdivd: goto default;
case Opcode.vsdivd: goto default;
case Opcode.vvaddl: goto default;
case Opcode.vsaddl: goto default;
case Opcode.vvaddg: goto default;
case Opcode.vsaddg: goto default;
case Opcode.vvaddf: goto default;
case Opcode.vsaddf: goto default;
case Opcode.vvaddd: goto default;
case Opcode.vsaddd: goto default;
case Opcode.vvsubl: goto default;
case Opcode.vssubl: goto default;
case Opcode.vvsubg: goto default;
case Opcode.vssubg: goto default;
case Opcode.vvsubf: goto default;
case Opcode.vssubf: goto default;
case Opcode.vvsubd: goto default;
case Opcode.vssubd: goto default;
case Opcode.vvcmpl: goto default;
case Opcode.vvsrll: goto default;
case Opcode.vscmpl: goto default;
case Opcode.vssrll: goto default;
case Opcode.vvcmpg: goto default;
case Opcode.vscmpg: goto default;
case Opcode.vvcmpf: goto default;
case Opcode.vvslll: goto default;
case Opcode.vscmpf: goto default;
case Opcode.vsslll: goto default;
case Opcode.vvcmpd: goto default;
case Opcode.vscmpd: goto default;
case Opcode.vvbisl: goto default;
case Opcode.vvxorl: goto default;
case Opcode.vsbisl: goto default;
case Opcode.vsxorl: goto default;
case Opcode.vvbicl: goto default;
case Opcode.vvcvt: goto default;
case Opcode.vsbicl: goto default;
case Opcode.iota: goto default;
case Opcode.vvmerge: goto default;
case Opcode.vsmerge: goto default;
case Opcode.bugl: goto default;
case Opcode.bugw: goto default;
}
yield return(new RtlInstructionCluster(
addr,
len,
rtlInstructions.ToArray())
{
Class = rtlc
});
}
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
var instr = dasm.Current;
this.rtlInstructions = new List <RtlInstruction>();
this.rtlc = RtlClass.Linear;
this.m = new RtlEmitter(rtlInstructions);
switch (instr.opcode)
{
default:
throw new AddressCorrelatedException(
instr.Address,
"Rewriting of MIPS instruction {0} not implemented yet.",
instr.opcode);
case Opcode.illegal:
rtlc = RtlClass.Invalid; m.Invalid(); break;
case Opcode.add:
case Opcode.addi:
case Opcode.addiu:
case Opcode.addu:
RewriteAdd(instr, PrimitiveType.Word32); break;
case Opcode.add_d: RewriteFpuBinopD(instr, m.FAdd); break;
case Opcode.and:
case Opcode.andi:
RewriteAnd(instr); break;
case Opcode.bc1f: RewriteBranchConditional1(instr, false); break;
case Opcode.bc1t: RewriteBranchConditional1(instr, true); break;
case Opcode.beq: RewriteBranch(instr, m.Eq, false); break;
case Opcode.beql: RewriteBranchLikely(instr, m.Eq); break;
case Opcode.bgez:
RewriteBranch0(instr, m.Ge, false); break;
case Opcode.bgezl:
RewriteBranch0(instr, m.Ge, true); break;
case Opcode.bgezal:
RewriteBranch0(instr, m.Ge, false); break;
case Opcode.bgezall:
RewriteBranch0(instr, m.Ge, true); break;
case Opcode.bgtz:
RewriteBranch0(instr, m.Gt, false); break;
case Opcode.bgtzl:
RewriteBranch0(instr, m.Gt, true); break;
case Opcode.blez:
RewriteBranch0(instr, m.Le, false); break;
case Opcode.blezl:
RewriteBranch0(instr, m.Le, true); break;
case Opcode.bltz:
RewriteBranch0(instr, m.Lt, false); break;
case Opcode.bltzl:
RewriteBranch0(instr, m.Lt, true); break;
case Opcode.bltzal:
RewriteBranch0(instr, m.Lt, true); break;
case Opcode.bltzall:
RewriteBranch0(instr, m.Lt, true); break;
case Opcode.bne:
RewriteBranch(instr, m.Ne, false); break;
case Opcode.bnel: RewriteBranchLikely(instr, m.Ne); break;
case Opcode.@break: RewriteBreak(instr); break;
case Opcode.c_le_d: RewriteFpuCmpD(instr, Operator.Fle); break;
case Opcode.c_le_s: RewriteFpuCmpD(instr, Operator.Fle); break;
case Opcode.c_lt_d: RewriteFpuCmpD(instr, Operator.Flt); break;
case Opcode.c_lt_s: RewriteFpuCmpD(instr, Operator.Flt); break;
case Opcode.c_eq_d: RewriteFpuCmpD(instr, Operator.Feq); break;
case Opcode.c_eq_s: RewriteFpuCmpD(instr, Operator.Feq); break;
case Opcode.cfc1: RewriteCfc1(instr); break;
case Opcode.ctc1: RewriteCtc1(instr); break;
case Opcode.cvt_d_l: RewriteCvtD(instr, PrimitiveType.Real64); break;
case Opcode.cvt_s_d: RewriteCvtD(instr, PrimitiveType.Real32); break;
case Opcode.cvt_w_d: RewriteCvtD(instr, PrimitiveType.Int32); break;
case Opcode.dadd:
case Opcode.daddi:
RewriteAdd(instr, PrimitiveType.Word64); break;
case Opcode.daddiu:
case Opcode.daddu: RewriteAdd(instr, PrimitiveType.Word64); break;
case Opcode.ddiv: RewriteDiv(instr, m.SDiv); break;
case Opcode.ddivu: RewriteDiv(instr, m.UDiv); break;
case Opcode.div: RewriteDiv(instr, m.SDiv); break;
case Opcode.divu: RewriteDiv(instr, m.UDiv); break;
case Opcode.div_d: RewriteFpuBinopD(instr, m.FDiv); break;
case Opcode.dmfc1: RewriteMfc1(instr); break;
case Opcode.dmtc1: RewriteMtc1(instr); break;
case Opcode.dmult: RewriteMul(instr, m.SMul, PrimitiveType.Int128); break;
case Opcode.dmultu: RewriteMul(instr, m.UMul, PrimitiveType.UInt128); break;
case Opcode.dsll: RewriteSll(instr); break;
case Opcode.dsll32: RewriteDshift32(instr, m.Shl); break;
case Opcode.dsllv: RewriteSrl(instr); break;
case Opcode.dsra: RewriteSra(instr); break;
case Opcode.dsra32: RewriteDshift32(instr, m.Sar); break;
case Opcode.dsrav: RewriteSra(instr); break;
case Opcode.dsrl: RewriteSrl(instr); break;
case Opcode.dsrl32: RewriteDshift32(instr, m.Shr); break;
case Opcode.dsrlv: RewriteSrl(instr); break;
case Opcode.dsub:
case Opcode.dsubu:
RewriteSub(instr, PrimitiveType.Word64); break;
case Opcode.j: RewriteJump(instr); break;
case Opcode.jal: RewriteJal(instr); break;
case Opcode.jalr: RewriteJalr(instr); break;
case Opcode.jr: RewriteJr(instr); break;
case Opcode.lb: RewriteLoad(instr, PrimitiveType.SByte); break;
case Opcode.lbu: RewriteLoad(instr, PrimitiveType.Byte); break;
case Opcode.ld: RewriteLoad(instr, PrimitiveType.Word64); break;
case Opcode.ldl: RewriteLdl(instr); break;
case Opcode.ldr: RewriteLdr(instr); break;
case Opcode.ldc1: RewriteLdc1(instr); break;
case Opcode.lh: RewriteLoad(instr, PrimitiveType.Int16); break;
case Opcode.lhu: RewriteLoad(instr, PrimitiveType.UInt16); break;
case Opcode.ll: RewriteLoadLinked32(instr); break;
case Opcode.lld: RewriteLoadLinked64(instr); break;
case Opcode.lui: RewriteLui(instr); break;
case Opcode.lw: RewriteLoad(instr, PrimitiveType.Int32); break;
case Opcode.lwc1: RewriteLoad(instr, PrimitiveType.Real32); break;
case Opcode.lwl: RewriteLwl(instr); break;
case Opcode.lwr: RewriteLwr(instr); break;
case Opcode.lwu: RewriteLoad(instr, PrimitiveType.UInt32); break;
case Opcode.mfc0: RewriteMfc0(instr); break;
case Opcode.mfc1: RewriteMfc1(instr); break;
case Opcode.mfhi: RewriteMf(instr, arch.hi); break;
case Opcode.mflo: RewriteMf(instr, arch.lo); break;
case Opcode.mthi: RewriteMt(instr, arch.hi); break;
case Opcode.mtlo: RewriteMt(instr, arch.lo); break;
case Opcode.movn: RewriteMovCc(instr, m.Ne0); break;
case Opcode.movz: RewriteMovCc(instr, m.Eq0); break;
case Opcode.mov_d: RewriteCopy(instr); break;
case Opcode.mov_s: RewriteCopy(instr); break;
case Opcode.mtc1: RewriteMtc1(instr); break;
case Opcode.mult: RewriteMul(instr, m.SMul, PrimitiveType.Int64); break;
case Opcode.multu: RewriteMul(instr, m.UMul, PrimitiveType.UInt64); break;
case Opcode.mul_s: RewriteMul(instr, m.FMul, PrimitiveType.Real32); break;
case Opcode.mul_d: RewriteMulD(instr); break;
case Opcode.nop: m.Nop(); break;
case Opcode.nor: RewriteNor(instr); break;
case Opcode.or:
case Opcode.ori: RewriteOr(instr); break;
case Opcode.pref:
goto default;
case Opcode.sb: RewriteStore(instr); break;
case Opcode.sc: RewriteStoreConditional32(instr); break;
case Opcode.scd: RewriteStoreConditional64(instr); break;
case Opcode.sd: RewriteStore(instr); break;
case Opcode.sdc1: RewriteStore(instr); break;
case Opcode.sdl: RewriteSdl(instr); break;
case Opcode.sdr: RewriteSdr(instr); break;
case Opcode.sh: RewriteStore(instr); break;
case Opcode.sll:
case Opcode.sllv:
RewriteSll(instr); break;
case Opcode.slt: RewriteSxx(instr, m.Lt); break;
case Opcode.slti: RewriteSxx(instr, m.Lt); break;
case Opcode.sltiu: RewriteSxx(instr, m.Ult); break;
case Opcode.sltu: RewriteSxx(instr, m.Ult); break;
case Opcode.sra:
case Opcode.srav:
RewriteSra(instr); break;
case Opcode.srl:
case Opcode.srlv:
RewriteSrl(instr); break;
case Opcode.sub:
case Opcode.subu:
RewriteSub(instr, PrimitiveType.Word32); break;
case Opcode.sub_d: RewriteFpuBinopD(instr, m.FSub); break;
case Opcode.sw:
case Opcode.swc1:
RewriteStore(instr); break;
case Opcode.swl: RewriteSwl(instr); break;
case Opcode.swr: RewriteSwr(instr); break;
case Opcode.sync: RewriteSync(instr); break;
case Opcode.syscall: RewriteSyscall(instr); break;
case Opcode.teq: RewriteTrap(instr, m.Eq); break;
case Opcode.tge: RewriteTrap(instr, m.Ge); break;
case Opcode.tgeu: RewriteTrap(instr, m.Uge); break;
case Opcode.tlt: RewriteTrap(instr, m.Lt); break;
case Opcode.tltu: RewriteTrap(instr, m.Ult); break;
case Opcode.tne: RewriteTrap(instr, m.Ne); break;
case Opcode.trunc_l_d: RewriteTrunc(instr, "trunc", PrimitiveType.Real64, PrimitiveType.Int64); break;
case Opcode.xor:
case Opcode.xori:
RewriteXor(instr); break;
case Opcode.rdhwr: RewriteReadHardwareRegister(instr); break;
}
yield return(new RtlInstructionCluster(
instr.Address,
4,
rtlInstructions.ToArray())
{
Class = rtlc
});
}
}
public RtlTransfer(Expression target, RtlClass rtlClass)
{
this.Target = target;
this.Class = rtlClass;
}
public RtlCall(Expression target, byte stackPushedReturnAddressSize, RtlClass rtlClass) : base(target, rtlClass)
{
Debug.Assert((rtlClass & (RtlClass.Call | RtlClass.Transfer)) != 0);
this.ReturnAddressSize = stackPushedReturnAddressSize;
}
/// <summary>
/// Generates a RtlBranch instruction which jumps to the address <paramref name="target"/>
/// if the boolean expression <paramref name="condition" /> is true. The <paramref name="rtlClass" />
/// can be used to indicate if there is a delay slot after this RTL instruction.
/// </summary>
/// <param name="condition">Boolean expression</param>
/// <param name="target">Control goes to this address if condition is true</param>
/// <param name="rtlClass">Describes details the branch instruction</param>
/// <returns>A reference to this RtlEmitter.</returns>
public RtlEmitter Branch(Expression condition, Address target, RtlClass rtlClass)
{
instrs.Add(new RtlBranch(condition, target, rtlClass));
return(this);
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
var addr = this.instr.Address;
this.rtlInstructions = new List <RtlInstruction>();
this.rtlc = RtlClass.Linear;
this.m = new RtlEmitter(rtlInstructions);
switch (dasm.Current.Opcode)
{
default:
host.Error(
instr.Address,
string.Format("PowerPC instruction '{0}' is not supported yet.", instr));
goto case Opcode.illegal;
case Opcode.illegal: rtlc = RtlClass.Invalid; m.Invalid(); break;
case Opcode.addi: RewriteAddi(); break;
case Opcode.addc: RewriteAddc(); break;
case Opcode.addic: RewriteAddic(); break;
case Opcode.addis: RewriteAddis(); break;
case Opcode.add: RewriteAdd(); break;
case Opcode.adde: RewriteAdde(); break;
case Opcode.addme: RewriteAddme(); break;
case Opcode.addze: RewriteAddze(); break;
case Opcode.and: RewriteAnd(false); break;
case Opcode.andc: RewriteAndc(); break;
case Opcode.andi: RewriteAnd(false); break;
case Opcode.andis: RewriteAndis(); break;
case Opcode.b: RewriteB(); break;
case Opcode.bc: RewriteBc(false); break;
case Opcode.bcctr: RewriteBcctr(false); break;
case Opcode.bctrl: RewriteBcctr(true); break;
case Opcode.bdnz: RewriteCtrBranch(false, false, m.Ne, false); break;
case Opcode.bdnzf: RewriteCtrBranch(false, false, m.Ne, false); break;
case Opcode.bdnzl: RewriteCtrBranch(true, false, m.Ne, false); break;
case Opcode.bdnzt: RewriteCtrBranch(false, false, m.Ne, true); break;
case Opcode.bdz: RewriteCtrBranch(false, false, m.Eq, false); break;
case Opcode.bdzf: RewriteCtrBranch(false, false, m.Eq, false); break;
case Opcode.bdzl: RewriteCtrBranch(true, false, m.Eq, false); break;
case Opcode.beq: RewriteBranch(false, false, ConditionCode.EQ); break;
case Opcode.beql: RewriteBranch(true, false, ConditionCode.EQ); break;
case Opcode.beqlr: RewriteBranch(false, true, ConditionCode.EQ); break;
case Opcode.beqlrl: RewriteBranch(true, true, ConditionCode.EQ); break;
case Opcode.bge: RewriteBranch(false, false, ConditionCode.GE); break;
case Opcode.bgel: RewriteBranch(true, false, ConditionCode.GE); break;
case Opcode.bgt: RewriteBranch(false, false, ConditionCode.GT); break;
case Opcode.bgtl: RewriteBranch(true, false, ConditionCode.GT); break;
case Opcode.bgtlr: RewriteBranch(false, true, ConditionCode.GT); break;
case Opcode.bl: RewriteBl(); break;
case Opcode.blr: RewriteBlr(); break;
case Opcode.ble: RewriteBranch(false, false, ConditionCode.LE); break;
case Opcode.blel: RewriteBranch(true, false, ConditionCode.LE); break;
case Opcode.blelr: RewriteBranch(false, true, ConditionCode.LE); break;
case Opcode.blelrl: RewriteBranch(true, true, ConditionCode.LE); break;
case Opcode.blt: RewriteBranch(false, false, ConditionCode.LT); break;
case Opcode.bltl: RewriteBranch(true, false, ConditionCode.LT); break;
case Opcode.bne: RewriteBranch(false, false, ConditionCode.NE); break;
case Opcode.bnel: RewriteBranch(true, false, ConditionCode.NE); break;
case Opcode.bnelr: RewriteBranch(false, true, ConditionCode.NE); break;
case Opcode.bns: RewriteBranch(false, false, ConditionCode.NO); break;
case Opcode.bnsl: RewriteBranch(true, false, ConditionCode.NO); break;
case Opcode.bso: RewriteBranch(false, false, ConditionCode.OV); break;
case Opcode.bsol: RewriteBranch(true, false, ConditionCode.OV); break;
case Opcode.cmp: RewriteCmp(); break;
case Opcode.cmpi: RewriteCmpi(); break;
case Opcode.cmpl: RewriteCmpl(); break;
case Opcode.cmpli: RewriteCmpli(); break;
case Opcode.cmplw: RewriteCmplw(); break;
case Opcode.cmplwi: RewriteCmplwi(); break;
case Opcode.cmpwi: RewriteCmpwi(); break;
case Opcode.cntlzd: RewriteCntlz("__cntlzd", PrimitiveType.Word64); break;
case Opcode.cntlzw: RewriteCntlz("__cntlzw", PrimitiveType.Word32); break;
case Opcode.creqv: RewriteCreqv(); break;
case Opcode.cror: RewriteCror(); break;
case Opcode.crnor: RewriteCrnor(); break;
case Opcode.crxor: RewriteCrxor(); break;
case Opcode.dcbt: RewriteDcbt(); break;
case Opcode.divw: RewriteDivw(); break;
case Opcode.divwu: RewriteDivwu(); break;
case Opcode.extsb: RewriteExts(PrimitiveType.SByte); break;
case Opcode.extsh: RewriteExts(PrimitiveType.Int16); break;
case Opcode.extsw: RewriteExts(PrimitiveType.Int32); break;
case Opcode.fadd: RewriteFadd(); break;
case Opcode.fadds: RewriteFadd(); break;
case Opcode.fcfid: RewriteFcfid(); break;
case Opcode.fctiwz: RewriteFctiwz(); break;
case Opcode.fcmpu: RewriteFcmpu(); break;
case Opcode.fdiv: RewriteFdiv(); break;
case Opcode.fdivs: RewriteFdiv(); break;
case Opcode.fmr: RewriteFmr(); break;
case Opcode.fmadd: RewriteFmadd(); break;
case Opcode.fmadds: RewriteFmadd(); break;
case Opcode.fmsubs: RewriteFmsub(); break;
case Opcode.fmul: RewriteFmul(); break;
case Opcode.fmuls: RewriteFmul(); break;
case Opcode.fneg: RewriteFneg(); break;
case Opcode.frsp: RewriteFrsp(); break;
case Opcode.fsub: RewriteFsub(); break;
case Opcode.fsubs: RewriteFsub(); break;
case Opcode.isync: RewriteIsync(); break;
case Opcode.lbz: RewriteLz(PrimitiveType.Byte); break;
case Opcode.lbzx: RewriteLzx(PrimitiveType.Byte); break;
case Opcode.lbzu: RewriteLzu(PrimitiveType.Byte); break;
case Opcode.lbzux: RewriteLzux(PrimitiveType.Byte); break;
case Opcode.ld: RewriteLz(PrimitiveType.Word64); break;
case Opcode.ldu: RewriteLzu(PrimitiveType.Word64); break;
case Opcode.lfd: RewriteLfd(); break;
case Opcode.lfs: RewriteLfs(); break;
case Opcode.lfsx: RewriteLzx(PrimitiveType.Real32); break;
case Opcode.lha: RewriteLha(); break;
case Opcode.lhax: RewriteLhax(); break;
case Opcode.lhau: RewriteLhau(); break;
case Opcode.lhaux: RewriteLhaux(); break;
case Opcode.lhz: RewriteLz(PrimitiveType.Word16); break;
case Opcode.lhzu: RewriteLzu(PrimitiveType.Word16); break;
case Opcode.lhzx: RewriteLzx(PrimitiveType.Word16); break;
case Opcode.lmw: RewriteLmw(); break;
case Opcode.lvewx: RewriteLvewx(); break;
case Opcode.lvlx: RewriteLvlx(); break;
case Opcode.lvsl: RewriteLvsl(); break;
case Opcode.lvx: RewriteLzx(PrimitiveType.Word128); break;
case Opcode.lwbrx: RewriteLwbrx(); break;
case Opcode.lwz: RewriteLz(PrimitiveType.Word32); break;
case Opcode.lwzu: RewriteLzu(PrimitiveType.Word32); break;
case Opcode.lwzx: RewriteLzx(PrimitiveType.Word32); break;
case Opcode.mcrf: RewriteMcrf(); break;
case Opcode.mfcr: RewriteMfcr(); break;
case Opcode.mfctr: RewriteMfctr(); break;
case Opcode.mftb: RewriteMftb(); break;
case Opcode.mffs: RewriteMffs(); break;
case Opcode.mflr: RewriteMflr(); break;
case Opcode.mfmsr: RewriteMfmsr(); break;
case Opcode.mfspr: RewriteMfspr(); break;
case Opcode.mtcrf: RewriteMtcrf(); break;
case Opcode.mtctr: RewriteMtctr(); break;
case Opcode.mtfsf: RewriteMtfsf(); break;
case Opcode.mtmsr: RewriteMtmsr(); break;
case Opcode.mtspr: RewriteMtspr(); break;
case Opcode.mtlr: RewriteMtlr(); break;
case Opcode.mulhw: RewriteMulhw(); break;
case Opcode.mulhwu: RewriteMulhwu(); break;
case Opcode.mulli: RewriteMull(); break;
case Opcode.mulld: RewriteMull(); break;
case Opcode.mullw: RewriteMull(); break;
case Opcode.neg: RewriteNeg(); break;
case Opcode.nand: RewriteAnd(true); break;
case Opcode.nor: RewriteOr(true); break;
case Opcode.or: RewriteOr(false); break;
case Opcode.orc: RewriteOrc(false); break;
case Opcode.ori: RewriteOr(false); break;
case Opcode.oris: RewriteOris(); break;
case Opcode.rfi: RewriteRfi(); break;
case Opcode.rldicl: RewriteRldicl(); break;
case Opcode.rlwinm: RewriteRlwinm(); break;
case Opcode.rlwimi: RewriteRlwimi(); break;
case Opcode.rlwnm: RewriteRlwnm(); break;
case Opcode.sc: RewriteSc(); break;
case Opcode.sld: RewriteSl(PrimitiveType.Word64); break;
case Opcode.slw: RewriteSl(PrimitiveType.Word32); break;
case Opcode.sradi: RewriteSra(); break;
case Opcode.sraw: RewriteSra(); break;
case Opcode.srawi: RewriteSra(); break;
case Opcode.srw: RewriteSrw(); break;
case Opcode.stb: RewriteSt(PrimitiveType.Byte); break;
case Opcode.stbu: RewriteStu(PrimitiveType.Byte); break;
case Opcode.stbux: RewriteStux(PrimitiveType.Byte); break;
case Opcode.stbx: RewriteStx(PrimitiveType.Byte); break;
case Opcode.std: RewriteSt(PrimitiveType.Word64); break;
case Opcode.stdu: RewriteStu(PrimitiveType.Word64); break;
case Opcode.stdx: RewriteStx(PrimitiveType.Word64); break;
case Opcode.stfd: RewriteSt(PrimitiveType.Real64); break;
case Opcode.stfiwx: RewriteStx(PrimitiveType.Int32); break;
case Opcode.stfs: RewriteSt(PrimitiveType.Real32); break;
case Opcode.sth: RewriteSt(PrimitiveType.Word16); break;
case Opcode.sthu: RewriteStu(PrimitiveType.Word16); break;
case Opcode.sthx: RewriteStx(PrimitiveType.Word16); break;
case Opcode.stmw: RewriteStmw(); break;
case Opcode.stvewx: RewriteStvewx(); break;
case Opcode.stvx: RewriteStx(PrimitiveType.Word128); break;
case Opcode.stw: RewriteSt(PrimitiveType.Word32); break;
case Opcode.stwbrx: RewriteStwbrx(); break;
case Opcode.stwu: RewriteStu(PrimitiveType.Word32); break;
case Opcode.stwux: RewriteStux(PrimitiveType.Word32); break;
case Opcode.stwx: RewriteStx(PrimitiveType.Word32); break;
case Opcode.subf: RewriteSubf(); break;
case Opcode.subfc: RewriteSubfc(); break;
case Opcode.subfe: RewriteSubfe(); break;
case Opcode.subfic: RewriteSubfic(); break;
case Opcode.subfze: RewriteSubfze(); break;
case Opcode.sync: RewriteSync(); break;
case Opcode.tw: RewriteTw(); break;
case Opcode.vaddfp: RewriteVaddfp(); break;
case Opcode.vadduwm: RewriteVadduwm(); break;
case Opcode.vand: RewriteAnd(false); break;
case Opcode.vandc: RewriteAndc(); break;
case Opcode.vcfsx: RewriteVct("__vcfsx", PrimitiveType.Real32); break;
case Opcode.vcmpgtfp: RewriteVcmpfp("__vcmpgtfp"); break;
case Opcode.vcmpgtuw: RewriteVcmpuw("__vcmpgtuw"); break;
case Opcode.vcmpeqfp: RewriteVcmpfp("__vcmpeqfp"); break;
case Opcode.vcmpequw: RewriteVcmpfp("__vcmpequw"); break;
case Opcode.vctsxs: RewriteVct("__vctsxs", PrimitiveType.Int32); break;
case Opcode.vmaddfp: RewriteVmaddfp(); break;
case Opcode.vmrghw: RewriteVmrghw(); break;
case Opcode.vmrglw: RewriteVmrglw(); break;
case Opcode.vnmsubfp: RewriteVnmsubfp(); break;
case Opcode.vperm: RewriteVperm(); break;
case Opcode.vrefp: RewriteVrefp(); break;
case Opcode.vrsqrtefp: RewriteVrsqrtefp(); break;
case Opcode.vsel: RewriteVsel(); break;
case Opcode.vsldoi: RewriteVsldoi(); break;
case Opcode.vslw: RewriteVslw(); break;
case Opcode.vspltisw: RewriteVspltisw(); break;
case Opcode.vspltw: RewriteVspltw(); break;
case Opcode.vsubfp: RewriteVsubfp(); break;
case Opcode.vxor: RewriteXor(); break;
case Opcode.xor: RewriteXor(); break;
case Opcode.xori: RewriteXor(); break;
case Opcode.xoris: RewriteXoris(); break;
}
yield return(new RtlInstructionCluster(addr, 4, this.rtlInstructions.ToArray())
{
Class = rtlc
});
}
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
var addr = dasm.Current.Address;
var len = dasm.Current.Length;
this.rtlInstructions = new List <RtlInstruction>();
this.rtlc = RtlClass.Linear;
this.m = new RtlEmitter(rtlInstructions);
switch (instr.opcode)
{
default:
host.Warn(
instr.Address,
"Rewriting of Risc-V instruction '{0}' not implemented yet.",
instr.opcode);
rtlc = RtlClass.Invalid;
m.Invalid();
break;
case Opcode.invalid: rtlc = RtlClass.Invalid; m.Invalid(); break;
case Opcode.add: RewriteAdd(); break;
case Opcode.addi: RewriteAdd(); break;
case Opcode.addiw: RewriteAddw(); break;
case Opcode.addw: RewriteAddw(); break;
case Opcode.and: RewriteAnd(); break;
case Opcode.andi: RewriteAnd(); break;
case Opcode.auipc: RewriteAuipc(); break;
case Opcode.beq: RewriteBranch(m.Eq); break;
case Opcode.bge: RewriteBranch(m.Ge); break;
case Opcode.bgeu: RewriteBranch(m.Uge); break;
case Opcode.blt: RewriteBranch(m.Lt); break;
case Opcode.bltu: RewriteBranch(m.Ult); break;
case Opcode.bne: RewriteBranch(m.Ne); break;
case Opcode.fcvt_d_s: RewriteFcvt(PrimitiveType.Real64); break;
case Opcode.feq_s: RewriteFcmp(PrimitiveType.Real32, m.FEq); break;
case Opcode.fmadd_s: RewriteFmadd(PrimitiveType.Real32, m.FAdd); break;
case Opcode.fmv_d_x: RewriteFcvt(PrimitiveType.Real64); break;
case Opcode.fmv_s_x: RewriteFcvt(PrimitiveType.Real32); break;
case Opcode.flw: RewriteFload(PrimitiveType.Real32); break;
case Opcode.jal: RewriteJal(); break;
case Opcode.jalr: RewriteJalr(); break;
case Opcode.lb: RewriteLoad(PrimitiveType.SByte); break;
case Opcode.lbu: RewriteLoad(PrimitiveType.Byte); break;
case Opcode.ld: RewriteLoad(PrimitiveType.Word64); break;
case Opcode.lh: RewriteLoad(PrimitiveType.Int16); break;
case Opcode.lhu: RewriteLoad(PrimitiveType.UInt16); break;
case Opcode.lui: RewriteLui(); break;
case Opcode.lw: RewriteLoad(PrimitiveType.Int32); break;
case Opcode.lwu: RewriteLoad(PrimitiveType.UInt32); break;
case Opcode.or: RewriteOr(); break;
case Opcode.ori: RewriteOr(); break;
case Opcode.sb: RewriteStore(PrimitiveType.Byte); break;
case Opcode.sd: RewriteStore(PrimitiveType.Word64); break;
case Opcode.sh: RewriteStore(PrimitiveType.Word16); break;
case Opcode.sw: RewriteStore(PrimitiveType.Word32); break;
case Opcode.slli: RewriteShift(m.Shl); break;
case Opcode.slliw: RewriteShiftw(m.Shl); break;
case Opcode.sllw: RewriteShiftw(m.Shl); break;
case Opcode.slt: RewriteSlt(false); break;
case Opcode.sltu: RewriteSlt(true); break;
case Opcode.srai: RewriteShift(m.Sar); break;
case Opcode.sraiw: RewriteShiftw(m.Sar); break;
case Opcode.srli: RewriteShift(m.Shr); break;
case Opcode.srliw: RewriteShiftw(m.Shr); break;
case Opcode.sub: RewriteSub(); break;
case Opcode.subw: RewriteSubw(); break;
case Opcode.xor: RewriteXor(); break;
case Opcode.xori: RewriteXor(); break;
}
yield return(new RtlInstructionCluster(
addr,
len,
rtlInstructions.ToArray())
{
Class = rtlc,
});
}
}
private void RewriteJmp()
{
rtlc = RtlClass.Transfer;
m.Goto(Operand(instr.op1));
}
private void RewriteRts()
{
rtlc = RtlClass.Transfer;
m.Return(2, 0);
}
private void RewriteReti()
{
rtlc = RtlClass.Transfer;
m.Return(2, 1);
}
private void RewriteBra()
{
rtlc = RtlClass.Transfer;
m.Goto(((AddressOperand)instr.Operands[0]).Address);
}
public IEnumerator <RtlInstructionCluster> GetEnumerator()
{
while (dasm.MoveNext())
{
this.instr = dasm.Current;
this.rtlc = RtlClass.Linear;
var rtls = new List <RtlInstruction>();
this.m = new RtlEmitter(rtls);
switch (instr.Opcode)
{
default:
host.Error(instr.Address, "Rewriting x86 opcode '{0}' is not supported yet.", instr);
rtlc = RtlClass.Invalid;
break;
case Opcode.adc: RewriteAdcSbb(m.IAdd); break;
case Opcode.add: RewriteArithmetic(m.IAdd); break;
case Opcode.and: RewriteLogical(m.And); break;
case Opcode.andp: RewriteLogical(m.And); break;
case Opcode.btjo: RewriteBtj(a => a); break;
case Opcode.btjop: RewriteBtj(a => a); break;
case Opcode.btjz: RewriteBtj(m.Comp); break;
case Opcode.btjzp: RewriteBtj(m.Comp); break;
case Opcode.br: RewriteBr(); break;
case Opcode.call: RewriteCall(); break;
case Opcode.clr: RewriteClr(); break;
case Opcode.tsta: RewriteTst(arch.a); break;
case Opcode.dac: RewriteDacDsb("__dac"); break;
case Opcode.dec: RewriteIncDec(m.ISub); break;
case Opcode.decd: RewriteIncdDecd(m.ISub); break;
case Opcode.dint: RewriteDint(); break;
case Opcode.djnz: RewriteDjnz(); break;
case Opcode.dsb: RewriteDacDsb("__dsb"); break;
case Opcode.eint: RewriteEint(); break;
case Opcode.idle: RewriteIdle(); break;
case Opcode.inc: RewriteIncDec(m.IAdd); break;
case Opcode.inv: RewriteInv(); break;
case Opcode.jmp: RewriteJmp(); break;
case Opcode.jeq: RewriteJcc(ConditionCode.EQ, FlagM.ZF); break;
case Opcode.jge: RewriteJcc(ConditionCode.GE, FlagM.NZ); break;
case Opcode.jgt: RewriteJcc(ConditionCode.GT, FlagM.NZ); break;
case Opcode.jhs: RewriteJcc(ConditionCode.UGE, FlagM.CF); break;
case Opcode.jl: RewriteJcc(ConditionCode.ULT, FlagM.CF); break;
case Opcode.jne: RewriteJcc(ConditionCode.EQ, FlagM.ZF); break;
case Opcode.lda: RewriteLda(); break;
case Opcode.ldsp: RewriteLdsp(); break;
case Opcode.mov: RewriteMov(); break;
case Opcode.movd: RewriteMovd(); break;
case Opcode.movp: RewriteMov(); break;
case Opcode.mpy: RewriteMpy(); break;
case Opcode.nop: m.Nop(); break;
case Opcode.or: RewriteLogical(m.Or); break;
case Opcode.orp: RewriteLogical(m.Or); break;
case Opcode.pop: RewritePop(); break;
case Opcode.push: RewritePush(); break;
case Opcode.reti: RewriteReti(); break;
case Opcode.rets: RewriteRets(); break;
case Opcode.rl: RewriteRotate(PseudoProcedure.Rol); break;
case Opcode.rlc: RewriteRotateC(PseudoProcedure.RolC); break;
case Opcode.rr: RewriteRotate(PseudoProcedure.Ror); break;
case Opcode.rrc: RewriteRotateC(PseudoProcedure.RorC); break;
case Opcode.sbb: RewriteAdcSbb(m.ISub); break;
case Opcode.setc: RewriteSetc(); break;
case Opcode.sta: RewriteSta(); break;
case Opcode.stsp: RewriteStsp(); break;
case Opcode.sub: RewriteArithmetic(m.ISub); break;
case Opcode.trap_0: RewriteTrap(0); break;
case Opcode.trap_1: RewriteTrap(1); break;
case Opcode.trap_2: RewriteTrap(2); break;
case Opcode.trap_3: RewriteTrap(3); break;
case Opcode.trap_4: RewriteTrap(4); break;
case Opcode.trap_5: RewriteTrap(5); break;
case Opcode.trap_6: RewriteTrap(6); break;
case Opcode.trap_7: RewriteTrap(7); break;
case Opcode.trap_8: RewriteTrap(8); break;
case Opcode.trap_9: RewriteTrap(9); break;
case Opcode.trap_10: RewriteTrap(10); break;
case Opcode.trap_11: RewriteTrap(11); break;
case Opcode.trap_12: RewriteTrap(12); break;
case Opcode.trap_13: RewriteTrap(13); break;
case Opcode.trap_14: RewriteTrap(14); break;
case Opcode.trap_15: RewriteTrap(15); break;
case Opcode.trap_16: RewriteTrap(16); break;
case Opcode.trap_17: RewriteTrap(17); break;
case Opcode.trap_18: RewriteTrap(18); break;
case Opcode.trap_19: RewriteTrap(19); break;
case Opcode.trap_20: RewriteTrap(20); break;
case Opcode.trap_21: RewriteTrap(21); break;
case Opcode.trap_22: RewriteTrap(22); break;
case Opcode.trap_23: RewriteTrap(23); break;
case Opcode.tstb: RewriteTst(arch.b); break;
case Opcode.xchb: RewriteXchb(); break;
case Opcode.xor: RewriteLogical(m.Xor); break;
case Opcode.xorp: RewriteLogical(m.Xor); break;
}
yield return(new RtlInstructionCluster(instr.Address, instr.Length, rtls.ToArray())
{
Class = rtlc,
});
}
}
public RtlInstruction Branch(Expression cond, Address target, RtlClass rtlClass)
{
var br = new RtlBranch(cond, target, rtlClass);
return Emit(br);
}
public RtlBranch(Expression condition, Address target, RtlClass rtlClass)
: base(target, rtlClass)
{
this.Condition = condition;
}
public RtlEmitter Branch(Expression condition, Address target, RtlClass rtlClass)
{
instrs.Add(new RtlBranch(condition, target, rtlClass));
return this;
}
private void EmitInvalid()
{
rtlInstructions.Clear();
rtlc = RtlClass.Invalid;
m.Invalid();
}
public RtlTransfer(Expression target, RtlClass rtlClass)
{
this.Target = target;
this.Class = rtlClass;
}
private void RewriteFabs()
{
rtlc = RtlClass.Linear;
var src = SrcOp(instr.op1, null);
var dst = DstOp(instr.op1, src, (a, b) => host.PseudoProcedure("fabs", src.DataType, b));
}
