protected override void DoCommandAction()
{
int slicePortIndex = 0;
foreach (LibElemInst inst in LibraryElementInstanceManager.Instance.GetAllInstantiations())
{
PortMapper portMapper = inst.PortMapper;
Slice s = FPGA.FPGA.Instance.GetSlice(inst.SliceName);
Tile clb = s.ContainingTile;
Tuple <string, string, PortMapper.MappingKind> mapping = portMapper.GetMappings().Where(m => Regex.IsMatch(m.Item2, SignalName)).FirstOrDefault();
string signalName = portMapper.GetSignalName(mapping.Item1);
int index = portMapper.GetIndex(mapping.Item1);
string netName = Prefix + signalName + "[" + index + "]";
Tuple <Port, Port> arc = clb.SwitchMatrix.GetAllArcs().FirstOrDefault(a => Regex.IsMatch(a.Item1.Name, SliceOutPorts[slicePortIndex]));
slicePortIndex++;
slicePortIndex %= SliceOutPorts.Count;
if (arc == null)
{
throw new ArgumentException("Cannot start pre route from tile " + clb.Location);
}
Location current = Navigator.GetDestinations(clb.Location, arc.Item2.Name).First();
bool startIsUserSelected = TileSelectionManager.Instance.IsUserSelected(current.Tile.TileKey, UserSelectionType);
bool continuePath = true;
string routingConstraint = @"set_property ROUTE { " + arc.Item1 + " " + arc.Item2 + " ";
do
{
Port port = current.Tile.SwitchMatrix.GetDrivenPorts(current.Pip).Where(p => Regex.IsMatch(p.Name, RoutingResources)).FirstOrDefault();
if (port == null)
{
throw new ArgumentException("Cannot continue pre route from " + current + ". Is the tile at the border of the device?");
}
routingConstraint += port.Name + " ";
current = Navigator.GetDestinations(current.Tile.Location, port.Name).FirstOrDefault();
continuePath =
(startIsUserSelected && TileSelectionManager.Instance.IsUserSelected(current.Tile.TileKey, UserSelectionType)) ||
(!startIsUserSelected && !TileSelectionManager.Instance.IsUserSelected(current.Tile.TileKey, UserSelectionType));
}while (continuePath);
routingConstraint += "} [get_nets " + netName + "]" + Environment.NewLine;;
routingConstraint += "set_property IS_ROUTE_FIXED TRUE [get_nets " + netName + "]";
OutputManager.WriteOutput(routingConstraint);
}
}
private void IntergrateIntoContainer(Command callee)
{
m_instanceCode.AppendLine("-- instantiation of " + m_instantation.InstanceName);
m_instanceCode.AppendLine(m_instantation.InstanceName + " : " + m_instantation.GetLibraryElement().PrimitiveName);
if (!string.IsNullOrEmpty(m_libraryElement.VHDLGenericMap))
{
m_instanceCode.AppendLine(m_libraryElement.VHDLGenericMap);
}
m_instanceCode.AppendLine("port map (");
List <string> mappings = new List <string>();
foreach (XDLPort port in ((XDLContainer)m_libraryElement.Containter).Ports)
{
if (!m_instantation.PortMapper.HasKindMapping(port.ExternalName))
{
callee.OutputManager.WriteOutput("Warning: Could not find a signal mapping for port " + port.ExternalName + ". Misspelled mapping? Note that the mapping is case sensitive.");
continue;
}
PortMapper mapper = m_instantation.PortMapper;
PortMapper.MappingKind mappingKind = mapper.GetMapping(port.ExternalName);
string rightHandSide = mapper.GetSignalName(port.ExternalName);
// do not vectorize already indeced ports
//bool vector = Regex.IsMatch(port.ExternalName, @"\d+$") && !Regex.IsMatch(rightHandSide, @"\(\d+\)$");
if (rightHandSide.Equals("0") || rightHandSide.Equals("1"))
{
mappings.Add("\t" + port.ExternalName + " => " + "'" + rightHandSide + "',");
}
else if (rightHandSide.Equals("open"))
{
mappings.Add("\t" + port.ExternalName + " => open,");
}
else if (!rightHandSide.Equals("open"))
{
VHDLSignalList signalList = null;
switch (mappingKind)
{
case PortMapper.MappingKind.NoVector:
case PortMapper.MappingKind.External:
{
// in case of entity signals add direction
signalList = m_container.Entity;
m_container.Entity.SetDirection(rightHandSide, port.Direction);
break;
}
case PortMapper.MappingKind.Internal:
{
signalList = m_container.SignalDeclaration;
break;
}
default:
throw new ArgumentException("Found port mapped to " + mappingKind + ". This mapping is not supported. Use either public or external, see command AddPortMapping");
}
if (!signalList.HasSignal(rightHandSide))
{
if (m_instantation.PortMapper.HasKindMapping(port.ExternalName))
{
signalList.Add(rightHandSide, 1, m_instantation.PortMapper.GetMapping(port.ExternalName));
}
else
{
signalList.Add(rightHandSide, 1);
}
}
switch (mappingKind)
{
case PortMapper.MappingKind.Internal:
case PortMapper.MappingKind.External:
{
//int index = signalList.GetSignalWidth(rightHandSide) - 1;
int index = mapper.GetIndex(port.ExternalName);
mappings.Add("\t" + port.ExternalName + " => " + rightHandSide + "(" + index + "),");
if (!signalList.HasSignal(rightHandSide))
{
signalList.Add(rightHandSide, -1);
}
if (signalList.GetSignalWidth(rightHandSide) <= index)
{
signalList.SetSignalWidth(rightHandSide, index + 1);
}
// store the index generated during VHDL generation for interface checks
//this.m_instantation.GetPortMapper().SetIndex(port.ExternalName, index);
break;
}
case PortMapper.MappingKind.NoVector:
{
mappings.Add("\t" + port.ExternalName + " => " + rightHandSide + ",");
break;
}
default:
throw new ArgumentException("Found port mapped to " + mappingKind + ". This mapping is not supported. Use either public or external, see command AddPortMapping");
}
}
}
if (mappings.Count > 0)
{
mappings[mappings.Count - 1] = Regex.Replace(mappings[mappings.Count - 1], ",$", "");
}
// update tool info
//Tile t = FPGA.FPGA.Instance.GetTile(m_instantation.AnchorLocation);
//Blackboard.Instance.ClearToolTipInfo(t);
foreach (string str in mappings)
{
m_instanceCode.AppendLine(str);
// update tool info
if (!str.EndsWith(" => ,"))
{
string toolTip = str;
toolTip = Regex.Replace(toolTip, @"^\s+", "");
toolTip = Regex.Replace(toolTip, ",", "");
toolTip += Environment.NewLine;
//Blackboard.Instance.AddToolTipInfo(t, toolTip);
}
}
m_instanceCode.AppendLine(");");
}
