private uint ExecuteARMInstruction(uint opcode, out bool swiInstruction) { swiInstruction = false; // Check if this op does not have a condition prefix if ((opcode & 0xF0000000) == 0xF0000000) { // It must be BLX(1) or an undefined instruction if ((opcode & 0xFE000000) == 0xFE000000) { return(blx1(opcode)); } return(DefaultInvalidOpCodeHandler(opcode)); } //Check condition code and execute it if the condition code allows if (!check_cc((byte)(opcode >> 28))) { return(1); } SWIFlag = false; uint cycleCount = ARMInstructionRegistry[opcode](opcode); swiInstruction = SWIFlag; return(cycleCount); }//ExecuteARMInstruction
private void RegisterARMInstructions() { ARMInstructionRegistry = new PlainARMInstructionRegistry(); //The opcodes are broken into groups roughly corresponding to the table //in ARMv7 A5.1 //Data ops RegisterARMDataOps(); //Load/Store ops (also some extra load/store ops from the Data Ops section like LDRH) RegisterARMLoadStoreOps(); //Multiple Load/Store (just LDM and STM and their variants) RegisterOpcode(0x08100000, 0xf1efffff, ldm, "LDM"); RegisterOpcode(0x08000000, 0xf1efffff, stm, "STM"); //Branch instructions (the handler is so simple that it's not worth breaking this group up) RegisterOpcode(0x0a000000, 0xf1ffffff, branch, "branch"); //FP coprocessor - 110x xxxx xx RegisterOpcode(0x0c000000, 0xf1ffffff, mFPP.Execute, "FPP (1)"); //FP coprocessor - 1110 xxxx xx RegisterOpcode(0x0e000000, 0xf0ffffff, mFPP.Execute, "FPP (2)"); //Everything in the 1111 xxxx xx range counts as SWI (which, at this point, means //"reserved for plugin"). RegisterOpcode(0x0f000000, 0xf0ffffff, delegate(uint opcode) { SWIFlag = true; return(0); }, "SWI"); }