public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm12 = opCode & 0xfff; int imm4 = (opCode >> 16) & 0xf; Immediate = (imm4 << 12) | imm12; }
public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rm = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x1F; ShiftType = (ShiftType)((opCode >> 11) & 3); }
public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 8) & 0x7; Rn = (opCode >> 8) & 0x7; Immediate = (opCode >> 0) & 0xff; IsRotated = false; }
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Extend64 = ((opCode >> 22) & 3) == 2; WBack = ((opCode >> 24) & 1) == 0; // The type is not valid for the Unsigned Immediate 12-bits encoding, // because the bits 11:10 are used for the larger Immediate offset. MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned; PostIdx = type == MemOp.PostIndexed; Unscaled = type == MemOp.Unscaled || type == MemOp.Unprivileged; // Unscaled and Unprivileged doesn't write back, // but they do use the 9-bits Signed Immediate. if (Unscaled) { WBack = false; } if (WBack || Unscaled) { // 9-bits Signed Immediate. Immediate = (opCode << 11) >> 23; } else { // 12-bits Unsigned Immediate. Immediate = ((opCode >> 10) & 0xfff) << Size; } }
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Immediate = (opCode >> 16) & 0x3f; var limm = ((opCode >> 1) & 0x40) | Immediate; if ((limm & 0x40) == 0b1000000) { Size = 3; Shift = Immediate; } else if ((limm & 0x60) == 0b0100000) { Size = 2; Shift = Immediate - 32; } else if ((limm & 0x70) == 0b0010000) { Size = 1; Shift = Immediate - 16; } else if ((limm & 0x78) == 0b0001000) { Size = 0; Shift = Immediate - 8; } else { Instruction = InstDescriptor.Undefined; } if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm)) { Instruction = InstDescriptor.Undefined; } }
public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Q = false; RegisterSize = RegisterSize.Simd64; int imm6 = (opCode >> 16) & 0x3f; if ((imm6 & 0x20) == 0b100000) { Size = 2; Shift = imm6 - 32; } else if ((imm6 & 0x30) == 0b010000) { Size = 1; Shift = imm6 - 16; } else if ((imm6 & 0x38) == 0b001000) { Size = 0; Shift = imm6 - 8; } else { Instruction = InstDescriptor.Undefined; } if (GetType() == typeof(OpCode32SimdShImmLong) && DecoderHelper.VectorArgumentsInvalid(true, Vd)) { Instruction = InstDescriptor.Undefined; } }
public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rn = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x7; IsRotated = false; }
public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c); ShiftType = (ShiftType)((opCode >> 4) & 3); }
public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Vd = (opCode >> 12) & 0xf; Vd |= (opCode >> 18) & 0x10; Q = ((opCode >> 6) & 0x1) > 0; int cMode = (opCode >> 8) & 0xf; int op = (opCode >> 5) & 0x1; long imm; imm = ((uint)opCode >> 0) & 0xf; imm |= ((uint)opCode >> 12) & 0x70; imm |= ((uint)opCode >> 17) & 0x80; (Immediate, Size) = OpCodeSimdHelper.GetSimdImmediateAndSize(cMode, op, imm); RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64; if (DecoderHelper.VectorArgumentsInvalid(Q, Vd)) { Instruction = InstDescriptor.Undefined; } }
public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 12) & 0xf; Rn = (opCode >> 16) & 0xf; SetFlags = ((opCode >> 20) & 1) != 0; }
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Shift = ((opCode >> 12) & 0x1) != 0; IntType = (IntType)((opCode >> 13) & 0x7); Rm = (opCode >> 16) & 0x1f; Extend64 = ((opCode >> 22) & 0x3) == 2; }
public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm4L = (opCode >> 0) & 0xf; int imm4H = (opCode >> 8) & 0xf; Immediate = imm4L | (imm4H << 4); }
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; Immediate = (opCode >> 7) & 0x1f; ShiftType = (ShiftType)((opCode >> 5) & 3); }
public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; Rs = (opCode >> 8) & 0xf; ShiftType = (ShiftType)((opCode >> 5) & 3); }
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = (opCode >> 8) & 0x3; bool single = Size != 3; if (single) { Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e); } else { Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf); } long imm; imm = ((uint)opCode >> 0) & 0xf; imm |= ((uint)opCode >> 12) & 0xf0; Immediate = (Size == 3) ? (long)DecoderHelper.Imm8ToFP64Table[(int)imm] : DecoderHelper.Imm8ToFP32Table[(int)imm]; RegisterSize = (!single) ? RegisterSize.Int64 : RegisterSize.Int32; Elems = 1; }
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm4 = (opCode >> 11) & 0xf; int imm5 = (opCode >> 16) & 0x1f; if (imm5 == 0b10000) { Instruction = InstDescriptor.Undefined; return; } Size = imm5 & -imm5; switch (Size) { case 1: Size = 0; break; case 2: Size = 1; break; case 4: Size = 2; break; case 8: Size = 3; break; } SrcIndex = imm4 >> Size; DstIndex = imm5 >> (Size + 1); }
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm6 = (opCode >> 16) & 0x3f; int limm6 = ((opCode >> 1) & 0x40) | imm6; if ((limm6 & 0x40) == 0b1000000) { Size = 3; Shift = imm6; } else if ((limm6 & 0x60) == 0b0100000) { Size = 2; Shift = imm6 - 32; } else if ((limm6 & 0x70) == 0b0010000) { Size = 1; Shift = imm6 - 16; } else if ((limm6 & 0x78) == 0b0001000) { Size = 0; Shift = imm6 - 8; } else { Instruction = InstDescriptor.Undefined; } if (GetType() == typeof(OpCode32SimdShImm) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm)) { Instruction = InstDescriptor.Undefined; } }
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0x1f; Immediate = DecoderHelper.DecodeImmS19_2(opCode); Immediate |= ((long)opCode >> 29) & 3; }
public OpCodeT16MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 0) & 7; Rn = (opCode >> 3) & 7; Rm = (opCode >> 6) & 7; IsLoad = ((opCode >> 9) & 7) >= 3; }
public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 12) & 0xf; Rn = (opCode >> 0) & 0xf; Msb = (opCode >> 16) & 0x1f; Lsb = (opCode >> 7) & 0x1f; }
public OpCodeT16BImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Cond = (Condition)((opCode >> 8) & 0xf); int imm = (opCode << 24) >> 23; Immediate = GetPc() + imm; }
public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = ((opCode >> 30) & 3) + 2; Extend64 = false; DecodeImm(opCode); }
public OpCodeT16Adr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 8) & 7; int imm = (opCode & 0xff) << 2; Immediate = (int)(GetPc() & 0xfffffffc) + imm; }
public OpCodeT16BImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 0) & 0x7; int imm = ((opCode >> 2) & 0x3e) | ((opCode >> 3) & 0x40); Immediate = (int)GetPc() + imm; }
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = opCode & 0x1f; Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode); Bit = (opCode >> 19) & 0x1f; Bit |= (opCode >> 26) & 0x20; }
public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 0) & 0xf; Imm5 = (opCode >> 7) & 0x1f; Rd = (opCode >> 12) & 0xf; SatImm = (opCode >> 16) & 0x1f; ShiftType = (ShiftType)((opCode >> 5) & 2); }
public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = 3; if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm, Vn)) { Instruction = InstDescriptor.Undefined; } }
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { // Currently, this instruction is treated as though it's OPCODE is the true size, // which lets us deal with reversing vectors on a single element basis (eg. math magic an I64 rather than insert lots of I8s). int tempSize = Size; Size = 3 - Opc; // Op 0 is 64 bit, 1 is 32 and so on. Opc = tempSize; }
public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = (opCode >> 18) & 0x3; if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm)) { Instruction = InstDescriptor.Undefined; } }
public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { var opc = (opCode >> 16) & 0xf; if ((opc & 0b1) == 1) { Size = 0; Index = (opc >> 1) & 0x7; }