static (ControlLines[], ControlLines2[]) IncReg16(HLBusReg16 reg)
{
return(new[]
{
// ADD L, 1
// L -> ATemp
(ReadLReg16(reg) | LBus2DBus | DBus2A | A2Alu | ATempLoad),
// Imm(1) -> BBus, ATemp -> ABus, ADD, UpdateFlags, AluRes -> L
(Imm2BBus | ATemp2ABus
| AluOpAdd | Alu2Flags | LoadAluFlags
| RBus2DBus | WriteLReg16(reg) | DBus2LBus).SetImmediate(1),
// ADC H, 0
// H -> ATemp
(ReadHReg16(reg) | HBus2DBus | DBus2A | A2Alu | ATempLoad),
// Imm(0) -> BBus, ATemp -> ABus, FlagsIn, ADD, UpdateFlags, AluRes -> H
(Imm2BBus | ATemp2ABus
| Flags2Alu | AluOpAdd | Alu2Flags | LoadAluFlags
| RBus2DBus | WriteHReg16(reg) | DBus2HBus
| TogglePhase).SetImmediate(0),
},
new[]
{
ControlLines2.None,
ControlLines2.None,
ControlLines2.None,
ControlLines2.None,
});
}
static (ControlLines[], ControlLines2[]) LdReg16Ind(HLBusReg16 target, HLBusReg16 ind)
{
return(new[]
{
ControlLines.None
},
new[]
{
ControlLines2.None
});
}
static (ControlLines[], ControlLines2[]) LdReg8Ind(HLBusReg8 target, HLBusReg16 ind)
{
return(new[]
{
(ReadReg16(ind) | ABufLoad),
(DBuf2DBus | DBus2Reg8(target)
| Write_ReadPinRead | BusEnablePin
| TogglePhase)
},
new[]
{
ControlLines2.None,
ControlLines2.None,
});
}
static (ControlLines[], ControlLines2[]) LdAInd(HLBusReg16 reg)
{
return(new[]
{
// HL -> ABuf
(ReadReg16(reg) | ABufLoad),
// D -> A, Write(Abuf)
(DBus2A | ALoad | DBuf2DBus | Write_ReadPinRead | BusEnablePin
| TogglePhase)
},
new[]
{
ControlLines2.None,
ControlLines2.None,
});
}
static (ControlLines[], ControlLines2[]) LdIndA(HLBusReg16 reg)
{
return(new[]
{
// HL -> ABuf
(ReadHReg16(reg) | ReadLReg16(reg) | ABufLoad),
// A -> D, Write(Abuf)
(A2DBus | AOut | DBus2DBuf | Write_ReadPinWrite | BusEnablePin
| TogglePhase)
},
new[]
{
ControlLines2.None,
ControlLines2.None,
});
}
static (ControlLines[], ControlLines2[]) LdReg16Abs(HLBusReg16 reg)
{
return(new[]
{
// this is a mixture of lda (WZ)
// ACBA + 1 -> ACBA, ACBA + 1 -> ABuf
// Read(Abuf), D -> W
(ACOpInc | ACRes2ACB | ACBALoad | ABufLoad
| BusEnablePin | Write_ReadPinRead | DBuf2DBus | DBus2Reg8(W)),
// ACBA + 1 -> PC
// Read(ABuf), D -> DBuf
(ACOpInc | ACRes2HLBus | WriteReg16(PC)
| BusEnablePin | Write_ReadPinRead | DBufLoad),
// DBuf -> LBus
// W -> HBus
// HLBus -> ABuf
// HLBus -> ACBA
(DBufOut | DBuf2DBus | DBus2LBus
| Reg2HBusSelW
| ABufLoad
| ACBALoad),
// D -> regH, Read(Abuf)
// ACBA + 1 -> Abuf
(WriteHReg16(reg) | DBus2HLBusSelH | DBus2HBus | DBuf2DBus
| Write_ReadPinRead | BusEnablePin
| ACRes2ACB | ACOpInc | ABufLoad),
// D -> regL, Read(Abuf)
(WriteLReg16(reg) | DBus2HLBusSelL | DBus2LBus | DBuf2DBus
| Write_ReadPinRead | BusEnablePin
| TogglePhase)
},
new[]
{
ControlLines2.None,
ControlLines2.None,
ControlLines2.None,
ControlLines2.None,
ControlLines2.None,
});
}
static ControlLines ReadLReg16(HLBusReg16 reg)
{
switch (reg)
{
case WZ:
return(ReadReg8(Z));
case BC:
return(ReadReg8(C));
case DE:
return(ReadReg8(E));
case HL:
return(ReadReg8(L));
case SP:
return(ReadReg8(SPl));
case PC:
return(ReadReg8(PCl));
case LR:
return(ReadReg8(LRl));
case IX:
return(ReadReg8(IXl));
case IY:
return(ReadReg8(IYl));
case IV:
return(ReadReg8(IVl));
default:
throw new ArgumentException(reg.ToString());
}
}
static ControlLines WriteHReg16(HLBusReg16 reg)
{
switch (reg)
{
case WZ:
return(WriteReg8(W));
case BC:
return(WriteReg8(B));
case DE:
return(WriteReg8(D));
case HL:
return(WriteReg8(H));
case SP:
return(WriteReg8(SPh));
case PC:
return(WriteReg8(PCh));
case LR:
return(WriteReg8(LRh));
case IX:
return(WriteReg8(IXh));
case IY:
return(WriteReg8(IYh));
case IV:
return(WriteReg8(IVh));
default:
throw new ArgumentException(reg.ToString());
}
}
static (ControlLines[], ControlLines2[]) LdReg16Imm16(HLBusReg16 reg)
{
return(new[]
{
// ACBA + 1 -> ACBA, ACBA + 1 -> ABuf
// Read(Abuf), D -> arg1
(ACOpInc | ACRes2ACB | ACBALoad | ABufLoad
| BusEnablePin | Write_ReadPinRead
| DBuf2DBus | DBus2HBus | WriteHReg16(reg)),
// ACBA + 1 -> PC
// Read(ABuf), D -> DBuf
(ACOpInc | ACRes2HLBus | HBus2RegSelPCh | LBus2RegSelPCl
| BusEnablePin | Write_ReadPinRead | DBufLoad),
// DBuf -> arg2
(DBufOut | DBuf2DBus | DBus2LBus | WriteLReg16(reg)
| TogglePhase)
},
new[]
{
ControlLines2.None,
ControlLines2.None,
ControlLines2.None,
});
}
static ControlLines WriteReg16(HLBusReg16 reg) => WriteHReg16(reg) | WriteLReg16(reg);
static ControlLines ReadReg16(HLBusReg16 reg) => ReadHReg16(reg) | ReadLReg16(reg);