public static void GenerateFloatingPointCores()
{
var ise = ISEDetector.DetectMostRecentISEInstallation();
DesignContext.Reset();
var fpu = new FPUWrapper(ise.VersionTag);
DesignContext.Instance.Elaborate();
var fpga = new XC6VLX240T_FF1156();
fpga.SpeedGrade = ESpeedGrade._2;
fpga.TopLevelComponent = fpu;
var proj = fpga.Synthesize("c:\\temp\\fputest", "fpu", null,
EFlowStep.HDLGen | EFlowStep.IPCores);
var flow = proj.ConfigureFlow(fpu);
flow.TRCE.ReportUnconstrainedPaths = true;
flow.Start(
EFlowStep.XST |
EFlowStep.NGDBuild |
EFlowStep.Map |
EFlowStep.PAR |
EFlowStep.TRCE);
proj.AwaitRunningToolsToFinish();
PerformanceRecord designRec;
ResourceRecord deviceRec;
flow.ParseResourceRecords(out designRec, out deviceRec);
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_CordicSqrt_Testbench tb = new TestHLS_CordicSqrt_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
var docproj = new DocumentationProject(@".\hdl_out_TestHLSSqrt_Cordic\doc");
var project = new XilinxProject(@".\hdl_out_TestHLSSqrt_Cordic", "TestHLSSqrt_Cordic");
project.ISEVersion = EISEVersion._13_2;
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
//project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
SynthesisEngine.Create(DesignContext.Instance, docproj).Synthesize(new DocumentationGenerator());
project.Save();
docproj.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestDesign1 td1 = new TestDesign1(3, 4);
FixedPointSettings.GlobalOverflowMode = EOverflowMode.Wrap;
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(20 * TestDesign1.ClockPeriod);
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_TestDesign1", "TestDesign1");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);;
project.Save();
DesignContext.Reset();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_PortAccess_Testbench tb = new TestHLS_PortAccess_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_TestHLS_PortAccess", "TestHLS_PortAccess");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.SkipIPCoreSynthesis = true;
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalDefaultRadix = 10;
var tb = new Test_SinCosLUT_Testbench(7, 8, 9, 0);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
DesignContext.Stop();
//XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_Test_SinCosLUT_Testbench", "Test_SinCosLUT_Testbench");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Virtex6);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc6vlx240t);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.ff1156);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._2);
project.PutProperty(EXilinxProjectProperties.PreferredLanguage, EHDL.VHDL);
project.SetVHDLProfile();
project.TwinProject = new ModelsimProject(@".\hdl_out_Test_SinCosLUT_Testbench", "Test_SinCosLUT_Testbench");
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(tb, codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_CFlow2_Testbench tb = new TestHLS_CFlow2_Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(100.0, ETimeUnit.us));
DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX75T_FF484 fpga = new XC6VLX75T_FF484()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = tb.DUT
};
fpga.Testbenches.Add(tb);
fpga.Synthesize(@".\hdl_out_TestHLS_CFlow2", "TestHLS_CFlow2");
var eng = SynthesisEngine.Create(
DesignContext.Instance, new DocumentationProject(@".\hdl_out_TestHLS_CFlow2\doc"));
eng.Synthesize(new DocumentationGenerator());
}
public void TestTime2()
{
DesignContext.Reset();
DesignContext.Instance.Resolution = Time.Create(1.0, ETimeUnit.ps);
var c = new TestComponent();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(Time.Create(3.0, ETimeUnit.ns));
Assert.IsTrue(c._ps1called, "Process1 was not executed.");
Assert.IsTrue(c._ps2called, "Process2 was not executed.");
}
public static void RunTest()
{
DesignContext.Reset();
Testbench tb = new Testbench();
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(101 * Testbench.ClockPeriod);
DesignContext.Instance.CompleteAnalysis();
VHDLGenerator codeGen = new VHDLGenerator();
DocumentationProject proj = new DocumentationProject("./doc");
SynthesisEngine.Create(DesignContext.Instance, proj).Synthesize(codeGen);
proj.Save();
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalArithSizingMode = EArithSizingMode.VHDLCompliant;
var a = SFix.FromDouble(1.0, 8, 10);
var b = SFix.FromDouble(2.0, 8, 10);
var c = SFix.FromDouble(3.0, 8, 10);
var d = SFix.FromDouble(4.0, 8, 10);
TestAddMul2 dut = new TestAddMul2()
{
Clk = new SLSignal(),
A = new Signal <SFix>()
{
InitialValue = a
},
B = new Signal <SFix>()
{
InitialValue = b
},
C = new Signal <SFix>()
{
InitialValue = c
},
D = new Signal <SFix>()
{
InitialValue = d
},
R = new Signal <SFix>()
{
InitialValue = a * b + c * d
}
};
DesignContext.Instance.Elaborate();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = dut
};
fpga.Synthesize(@".\hdl_out_TestAddMul2", "TestAddMul2");
}
public static void RunTest()
{
DesignContext.Reset();
FixedPointSettings.GlobalArithSizingMode = EArithSizingMode.InSizeIsOutSize;
var design = new TestHLS_SFixDiv(8, 32);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(1.0, ETimeUnit.us));
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = design
};
fpga.Testbenches.Add(design);
fpga.Synthesize(@".\hdl_out_TestHLS_SFixDiv", "TestHLS_SFixDiv");
}
public static void Run()
{
DesignContext.Reset();
ALUTestDesign td = new ALUTestDesign(8, 8, 2);
DesignContext.Instance.Elaborate();
DesignContext.Instance.Simulate(new Time(0.5, ETimeUnit.us));
// Now convert the design to VHDL and embed it into a Xilinx ISE project
XilinxProject project = new XilinxProject(@".\hdl_out_ALUTestDesign", "ALUTestDesign");
project.PutProperty(EXilinxProjectProperties.DeviceFamily, EDeviceFamily.Spartan3);
project.PutProperty(EXilinxProjectProperties.Device, EDevice.xc3s1500l);
project.PutProperty(EXilinxProjectProperties.Package, EPackage.fg676);
project.PutProperty(EXilinxProjectProperties.SpeedGrade, ESpeedGrade._4);
project.SetVHDLProfile();
VHDLGenerator codeGen = new VHDLGenerator();
SynthesisEngine.Create(DesignContext.Instance, project).Synthesize(codeGen);
project.Save();
}
public static void RunTest()
{
DesignContext.Reset();
TestHLS_VanDerPol_Testbench tb = new TestHLS_VanDerPol_Testbench();
DesignContext.Instance.Elaborate();
//DesignContext.Instance.Simulate(new Time(4.0, ETimeUnit.us));
//DesignContext.Stop();
XilinxIntegration.RegisterIPCores(DesignContext.Instance.Descriptor);
DesignContext.Instance.CompleteAnalysis();
XC6VLX240T_FF1156 fpga = new XC6VLX240T_FF1156()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = tb.DUT
};
fpga.Testbenches.Add(tb);
fpga.Pins["J9"].Map(tb.DUT.Clk);
fpga.Synthesize(@".\hdl_out_TestHLS_VanDerPol", "TestHLS_VanDerPol");
}
public static void RunTest()
{
DesignContext.Reset();
RegPipe dut = new RegPipe(100, 32, true)
{
Clk = new SLSignal(),
Din = new SLVSignal(32),
Dout = new SLVSignal(32),
En = new SLSignal()
};
DesignContext.Instance.Elaborate();
var fpga = new DefaultXilinxDevice()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = dut
};
fpga.SetDevice(EDevice.xc5vlx110t);
fpga.SetPackage(EPackage.ff1136);
fpga.SpeedGrade = ESpeedGrade._2;
fpga.Synthesize(@"c:\temp\RegPipeTest", "RegPipeTest",
new ModelsimProject(@"c:\temp\RegPipeTest", "RegPipeTest"));
}
