public PIM(ref InsPartition ins_p_) { if (Config.DEBUG_PIM) { DEBUG.WriteLine("PIM Module Initialed."); } ins_p = ins_p_; unit = new List <ComputationalUnit>(); if (PIMConfigs.unit_type == PIM_Unit_Type.Processors) { if (Config.DEBUG_PIM) { DEBUG.WriteLine("PIM Unit Type : Processors."); } for (int i = 0; i < PIMConfigs.N; i++) { var p = new PIMProc(ref ins_p, i); unit.Add(p); } } else { if (Config.DEBUG_PIM) { DEBUG.WriteLine("PIM Unit Type : Pipeline."); } //pipeline mode // When PIMSim runs into pipeline mode, input should always be a Function. for (int i = 0; i < PIMConfigs.CU_Name.Count; i++) { if (PIMConfigs.CU_Name[i] == "Customied") { //add your code here } else { if (PIMConfigs.CU_Name[i] == "Adder") { unit.Add(new Adder(i, ref ins_p) as ComputationalUnit); return; } else { if (PIMConfigs.CU_Name[i] == "Adder_Conventional") { unit.Add(new Adder_Conventional(i, ref ins_p) as ComputationalUnit); return; } else { DEBUG.Error("No PIM Unit templates."); Environment.Exit(2); } } } } } }
public void PrintStatus() { DEBUG.WriteLine(); DEBUG.WriteLine(); DEBUG.WriteLine("++++++++++++++++++++++ Statistics ++++++++++++++++++++"); DEBUG.WriteLine(); DEBUG.WriteLine(); foreach (var item in proc) { item.PrintStatus(); } Mctrl.PrintStatus(); if (Config.use_pim) { PIMMctrl.PrintStatus(); } ins_p.PrintStatus(); foreach (var item in pim.unit) { item.PrintStatus(); } }
public void actual_update() { if (currentClockCycle == 0) { InitOutputFiles(traceFilename); if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("DEBUG : DRAMSim2 Clock Frequency =" + clockDomainCrosser.clock1 + "Hz, CPU Clock Frequency=" + clockDomainCrosser.clock2 + "Hz"); } } if (currentClockCycle % Config.dram_config.EPOCH_LENGTH == 0) { for (int i = 0; i < Config.dram_config.NUM_CHANS; i++) { channels[i].printStats(false); } } for (int i = 0; i < Config.dram_config.NUM_CHANS; i++) { channels[i].update(); } currentClockCycle++; }
public bool isEmpty(uint rank) { if (Config.dram_config.queuingStructure == QueuingStructure.PerRank) { return(queues[(int)rank][0].Count() <= 0); } else if (Config.dram_config.queuingStructure == QueuingStructure.PerRankPerBank) { for (int i = 0; i < Config.dram_config.NUM_BANKS; i++) { if (!(queues[(int)rank][(int)i].Count() <= 0)) { return(false); } } return(true); } else { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("DEBUG: Invalid Queueing Stucture"); } Environment.Exit(1); return(false); } }
public void powerUp() { if (!isPowerDown) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("== Error - Trying to power up rank " + id + " while it is not already powered down"); } Environment.Exit(1); } isPowerDown = false; for (int i = 0; i < Config.dram_config.NUM_BANKS; i++) { if (bankStates[i].nextPowerUp > currentClockCycle) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("== Error - Trying to power up rank " + id + " before we're allowed to"); } if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(bankStates[i].nextPowerUp + " " + currentClockCycle); } Environment.Exit(1); } bankStates[i].nextActivate = currentClockCycle + Config.dram_config.tXP; bankStates[i].currentBankState = CurrentBankState.Idle; } }
/// <summary> /// Add to MSHR /// </summary> /// <param name="req_">Processor Request</param> /// <returns>False when MSHR is full; else true.</returns> public bool add_to_mshr(ProcRequest req_) { if (MSHR.Exists(x => x.actual_addr == req_.actual_addr && x.block_addr == req_.block_addr)) { for (int i = 0; i < MSHR.Count; i++) { if (MSHR[i].actual_addr == req_.actual_addr && MSHR[i].block_addr == req_.block_addr) { if (Config.DEBUG_PROC) { DEBUG.WriteLine("-- MSHR : Merge Reqs : [" + req_.type + "] [0x" + req_.actual_addr.ToString("X") + "]"); } return(true); } } } if (MSHR.Count > Config.mshr_size) { if (Config.DEBUG_PROC) { DEBUG.WriteLine("-- MSHR : Failed to add Req to MSHR."); } mshr_stalled++; return(false); } mshr_loaded++; MSHR.Add(req_); if (Config.DEBUG_PROC) { DEBUG.WriteLine("-- MSHR : New Entry : [" + req_.type + "] [0x" + req_.actual_addr.ToString("X") + "]"); } return(true); }
public uint findChannelNumber(UInt64 addr) { // Single channel case is a trivial shortcut case if (Config.dram_config.NUM_CHANS == 1) { return(0); } if (!isPowerOfTwo(Config.dram_config.NUM_CHANS)) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR We can only support power of two # of channels.\n" + "I don't know what Intel was thinking, but trying to address map half a bit is a neat trick that we're not sure how to do"); } Environment.Exit(1); } // only chan is used from this set int channelNumber = 0, rank = 0, bank = 0, row = 0, col = 0; addressMapping(addr, ref channelNumber, ref rank, ref bank, ref row, ref col); if (channelNumber >= Config.dram_config.NUM_CHANS) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR Got channel index " + channelNumber + " but only " + Config.dram_config.NUM_CHANS + " exist"); } Environment.Exit(1); } //DEBUG("Channel idx = "<<channelNumber<<" totalbits="<<totalBits<<" channelbits="<<channelBits); return((uint)channelNumber); }
/// <summary> /// Search for a cacheline in cache. /// </summary> /// <param name="block_addr_">target block address</param> /// <param name="reqt_">related request type</param> /// <returns></returns> public bool search_block(UInt64 block_addr_, RequestType reqt_) { cycle++; UInt64 index = block_addr_ % (uint)max_set; for (int i = 0; i < assoc; i++) { if (cache[i, index].block_addr == block_addr_) { //cache hit hits++; cache[i, index].timestamp = cycle; if (reqt_ == RequestType.WRITE) { cache[i, index].dirty = true; } if (Config.DEBUG_CACHE) { DEBUG.WriteLine("-- L1Cache : Hit : [" + reqt_ + "] [0x" + block_addr_.ToString("X") + "]"); } return(true); } } //found none in cache miss++; if (Config.DEBUG_CACHE) { DEBUG.WriteLine("-- L1Cache : Miss : [" + reqt_ + "] [0x" + block_addr_.ToString("X") + "]"); } return(false); }
public string FilenameWithNumberSuffix(string filename, string extension, uint maxNumber = 100) { string currentFilename = filename + extension; if (!fileExists(currentFilename)) { return(currentFilename); } // otherwise, add the suffixes and test them out until we find one that works StringBuilder tmpNum = new StringBuilder(); tmpNum.Append(".");//<<1; for (uint i = 1; i < maxNumber; i++) { currentFilename = filename + tmpNum.ToString() + extension; if (fileExists(currentFilename)) { currentFilename = filename; //tmpNum.seekp(0); //tmpNum << "." << i; } else { return(currentFilename); } } // if we can't find one, just give up and return whatever is the current filename if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR Warning: Couldn't find a suitable suffix for " + filename); } return(currentFilename); }
/// <summary> /// l1Cache replace implement /// </summary> /// <param name="assoc">cache assoc</param> /// <param name="index">cache index</param> /// <param name="cache_">cache</param> /// <param name="ret_assoc">counted replace assoc index</param> /// <returns></returns> public override bool Calculate_Rep(int assoc, int index, CacheEntity[,] cache_, ref int ret_assoc) { int min_index = -1; UInt64 timestamp = UInt64.MaxValue; for (int i = 0; i < assoc; i++) { if (cache_[i, index].block_addr == NULL) { ret_assoc = i; return(false); } if (cache_[i, index].timestamp < timestamp) { min_index = i; timestamp = cache_[i, index].timestamp; } } if (min_index != -1) { ret_assoc = min_index; return(true); } //found no suitable replacement DEBUG.WriteLine("ERROR : No suitable replacement found."); return(false); }
public MultiChannelMemorySystem(string systemIniFilename_, uint megsOfMemory_) { megsOfMemory = megsOfMemory_; systemIniFilename = systemIniFilename_; // clockDomainCrosser = (new ClockDomain::Callback<MultiChannelMemorySystem, void>(this, &MultiChannelMemorySystem::actual_update)); clockDomainCrosser = new ClockDomainCrosser(new ClockUpdateCB(this.actual_update)); currentClockCycle = 0; if (!isPowerOfTwo(megsOfMemory)) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR: Please specify a power of 2 memory size"); } Environment.Exit(1); } if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("DEBUG: == Loading system model file '" + systemIniFilename + "' == "); } channels = new List <MemorySystem>(); for (uint i = 0; i < Config.dram_config.NUM_CHANS; i++) { MemorySystem channel = new MemorySystem(i, megsOfMemory / Config.dram_config.NUM_CHANS, ref dramsim_log); channels.Add(channel); } }
/// <summary> /// Print Statistics Info /// </summary> public static void PrintStatus() { DEBUG.WriteLine("--------------- MTRL [" + id + "] Statistics -----------"); DEBUG.WriteLine(" Total reqs added : " + total_add); DEBUG.WriteLine(" Total regs stalled : " + add_failed); DEBUG.WriteLine(" Total Stalled by Coherence :" + stalled_reqs_by_coherence); DEBUG.WriteLine(); }
/// <summary> /// Feed'n instructions to ALU. /// </summary> /// <param name="ins_"></param> public void add_ins(Instruction ins_) { total_loaded++; if (Config.DEBUG_ALU) { DEBUG.WriteLine("-- ALU : Feed Insts : " + ins_.ToString()); } ins.Enqueue(new KeyValuePair <ulong, Instruction>(cycle, ins_)); }
public override void PrintStatus() { DEBUG.WriteLine("---------------- PIM Unit [" + name + "] Statistics -------------"); DEBUG.WriteLine(); DEBUG.WriteLine(" Total Functions served : " + total_load); DEBUG.WriteLine(" Average latency : " + avg_latency); DEBUG.WriteLine(" Internal Bandwidth : " + interal_bandwidth + " MB/s"); DEBUG.WriteLine(); }
private void Usage() { DEBUG.WriteLine("PIMSim Usage:"); DEBUG.WriteLine("PIMSim -t tracefilepath -config configfilepath –o outputfile –n processorcount –c cycle"); DEBUG.WriteLine(" -t, -trace FILEPATH specify the path folder of input trace."); DEBUG.WriteLine(" -config FILEPATH specify the path folder of input configs."); DEBUG.WriteLine(" -o, -output FILENAME specify the file name of output file."); DEBUG.WriteLine(" -n, -N PROCCOUNT specify the count of host proc."); DEBUG.WriteLine(" -c, -cycle CYCLES specify the execution cycles ."); }
/// <summary> /// Added instructions to INS_W. /// </summary> /// <param name="ins_">added instructions</param> /// <param name="cycle_">added cycle</param> public void add_ins(Instruction ins_, UInt64 cycle_) { if (Config.DEBUG_PROC) { DEBUG.WriteLine("-- InsWd : Added Insts : " + ins_.ToString() + " "); } ins_.served_cycle = cycle_; ins.Add(ins_); total_loaded++; }
public MemorySystem(uint id, uint megsOfMemory, ref Stream dramsim_log_) { dramsim_log = dramsim_log_; ReturnReadData = null; WriteDataDone = null; currentClockCycle = 0; if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("===== MemorySystem " + systemID + " ====="); } UInt64 megsOfStoragePerRank = ((((UInt64)Config.dram_config.NUM_ROWS * (Config.dram_config.NUM_COLS * Config.dram_config.DEVICE_WIDTH) * Config.dram_config.NUM_BANKS) * ((UInt64)Config.dram_config.JEDEC_DATA_BUS_BITS / Config.dram_config.DEVICE_WIDTH)) / 8) >> 20; // If this is set, effectively override the number of ranks if (megsOfMemory != 0) { Config.dram_config.NUM_RANKS = (uint)(megsOfMemory / megsOfStoragePerRank); Config.dram_config.NUM_RANKS_LOG = Config.dram_config.log2(Config.dram_config.NUM_RANKS); if (Config.dram_config.NUM_RANKS == 0) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("WARNING: Cannot create memory system with " + megsOfMemory + "MB, defaulting to minimum size of " + megsOfStoragePerRank + "MB"); } Config.dram_config.NUM_RANKS = 1; } } Config.dram_config.NUM_DEVICES = Config.dram_config.JEDEC_DATA_BUS_BITS / Config.dram_config.DEVICE_WIDTH; Config.dram_config.TOTAL_STORAGE = (Config.dram_config.NUM_RANKS * megsOfStoragePerRank); if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("CH. " + systemID + " TOTAL_STORAGE : " + Config.dram_config.TOTAL_STORAGE + "MB | " + Config.dram_config.NUM_RANKS + " Ranks | " + Config.dram_config.NUM_DEVICES + " Devices per rank"); } memoryController = new MemoryController(this, dramsim_log); // TODO: change to other vector constructor? ranks = new List <Rank>(); for (int i = 0; i < Config.dram_config.NUM_RANKS; i++) { Rank r = new Rank(dramsim_log); r.setId(i); r.attachMemoryController(memoryController); ranks.Add(r); } memoryController.attachRanks(ranks); }
public HMCMem(int id_) { this.id = id_; hmc = new HMCSim(); hmc.hmcsim_init(Config.hmc_config.num_devs, Config.hmc_config.num_links, Config.hmc_config.num_vaults, Config.hmc_config.queue_depth, Config.hmc_config.num_banks, Config.hmc_config.num_drams, Config.hmc_config.capacity, Config.hmc_config.xbar_depth); if (Config.hmc_config.num_devs > 1) { /* -- TODO */ } else { /* * single device, connect everyone * */ for (int i = 0; i < Config.hmc_config.num_links; i++) { current_statue = hmc.hmcsim_link_config( (Config.hmc_config.num_devs + 1), 0, (uint)i, (uint)i, hmc_link_def.HMC_LINK_HOST_DEV); if (current_statue != 0) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR : "); } Environment.Exit(1); } else { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("SUCCESS : INITIALIZED LINK " + i); } } } } hmc.hmcsim_util_set_all_max_blocksize(Config.hmc_config.bsize); fs = new FileStream("out.txt", FileMode.OpenOrCreate); hmc.hmcsim_trace_handle(ref fs); hmc.hmcsim_trace_level((Macros.HMC_TRACE_BANK | Macros.HMC_TRACE_QUEUE | Macros.HMC_TRACE_CMD | Macros.HMC_TRACE_STALL | Macros.HMC_TRACE_LATENCY)); TransationQueue = new List <MemRequest>(); }
/// <summary> /// Print current status. /// </summary> public void PrintStatus() { DEBUG.WriteLine("=====================SpinLock Statistics====================="); DEBUG.WriteLine(); DEBUG.WriteLine(" Total Requests Served : " + total_request); DEBUG.WriteLine(" SetLock Requests : " + total_set_lock); DEBUG.WriteLine(" GetLock Requests : " + total_get_lock); DEBUG.WriteLine(" UnLock Requests : " + total_unlock); DEBUG.WriteLine(" Total stalled/Unstalled : " + total_stalled + "/" + total_unstalled); DEBUG.WriteLine(); }
public BusPacketType getBusPacketType() { switch (transactionType) { case TransactionType.DATA_READ: if (Config.dram_config.rowBufferPolicy == RowBufferPolicy.ClosePage) { return(BusPacketType.READ_P); } else if (Config.dram_config.rowBufferPolicy == RowBufferPolicy.OpenPage) { return(BusPacketType.READ); } else { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR: Unknown row buffer policy"); } Environment.Exit(1); } break; case TransactionType.DATA_WRITE: if (Config.dram_config.rowBufferPolicy == RowBufferPolicy.ClosePage) { return(BusPacketType.WRITE_P); } else if (Config.dram_config.rowBufferPolicy == RowBufferPolicy.OpenPage) { return(BusPacketType.WRITE); } else { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR: Unknown row buffer policy"); } Environment.Exit(1); } break; default: if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("ERROR: This transaction type doesn't have a corresponding bus packet type"); } Environment.Exit(1); break; } Environment.Exit(1); return(BusPacketType.DATA); }
/// <summary> /// Add to Cache /// Foreach requests, add lantency /// </summary> /// <param name="req_">Processor Request</param> /// <param name="if_shared"> if shared cache</param> public void add_to_cache(ProcRequest req_, bool if_shared = false) { req_.ts_departure = cycle + (if_shared ? Config.share_cache_hit_latecy : Config.l1cache_hit_latency); cache_req_queue.Enqueue(req_); curr_ins.ready = false; curr_ins.is_mem = true; if (Config.DEBUG_PROC) { DEBUG.WriteLine("CPU [" + this.pid + "] : Add Reqs to Cache_Queue : [" + req_.type + "] [0x" + req_.actual_addr.ToString("X") + "]"); } ins_w.add_ins(curr_ins, this.cycle); }
/// <summary> /// Write Complete Callback /// </summary> /// <param name="block_addr">Block address</param> public bool handle_writeback_queue() { if (writeback_req.Count <= 0) { return(false); } if (Config.DEBUG_PIM) { DEBUG.WriteLine("--PIM Proc : Served WriteBack Reqs : [" + writeback_req[0].type + "] [0x" + writeback_req[0].actual_addr.ToString("X") + "]"); } ProcRequest req = writeback_req[0]; return(mctrl.add_to_mctrl(req)); }
/// <summary> /// Set value by name /// </summary> /// <param name="name"></param> /// <param name="value"></param> /// <returns></returns> public static bool SetValue(string name, object value) { try { var s = typeof(Config).GetField(name).GetValue(name); typeof(Config).GetField(name).SetValue(name, Convert.ChangeType(value, s.GetType())); } catch { DEBUG.WriteLine("WARNING: Failed to set Parms:" + name + " = " + value.ToString() + ", plz check if necessary."); return(false); } return(true); }
public override void update() { // An outgoing packet is one that is currently sending on the bus // do the book keeping for the packet's time left on the bus if (outgoingDataPacket != null) { dataCyclesLeft--; if (dataCyclesLeft == 0) { //if the packet is done on the bus, call receiveFromBus and free up the bus memoryController.receiveFromBus(ref outgoingDataPacket); outgoingDataPacket = null; } } // decrement the counter for all packets waiting to be sent back for (int i = 0; i < readReturnCountdown.Count(); i++) { readReturnCountdown[i]--; } if (readReturnCountdown.Count() > 0 && readReturnCountdown[0] == 0) { // RL time has passed since the read was issued; this packet is // ready to go out on the bus outgoingDataPacket = readReturnPacket[0]; dataCyclesLeft = Config.dram_config.BL / 2; // remove the packet from the ranks // readReturnPacket.erase(readReturnPacket.begin()); readReturnPacket.RemoveAt(0); // readReturnCountdown.erase(readReturnCountdown.begin()); readReturnCountdown.RemoveAt(0); if (Config.dram_config.DEBUG_BUS) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(" -- R" + this.id + " Issuing On Data Bus : "); } outgoingDataPacket.print(); if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(); } } } }
/// <summary> /// Check if the same instructions had been loaded. /// </summary> /// <param name="block_addr_">target block address</param> /// <returns></returns> public bool if_exist(UInt64 block_addr_) { foreach (Instruction x in ins) { if (x.address == block_addr_ && x.is_mem) { if (Config.DEBUG_PROC) { DEBUG.WriteLine("-- InsWd : Hit : [0x" + block_addr_.ToString("X") + "]"); } return(true); } } return(false); }
public void printStats(bool finalStats = false) { for (int i = 0; i < Config.dram_config.NUM_CHANS; i++) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("==== Channel [" + i + "] ===="); } channels[i].printStats(finalStats); if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("//// Channel [" + i + "] ////"); } } }
/// <summary> /// Things ctrl done every cycle. /// </summary> public static void Step() { cycle++; if (Config.DEBUG_MTRL) { DEBUG.WriteLine(); DEBUG.WriteLine("---------PIM Memory Controller [" + id + "] Update [Cycle " + cycle + "]------------"); } for (int i = 0; i < wait_queue.Count(); i++) { ProcRequest peek = wait_queue[i]; if (peek.cycle + (UInt64)Config.mc_latency <= cycle - 1) { if (Config.DEBUG_MTRL) { DEBUG.WriteLine("-- Issue ProcRequest : [" + peek.type + "] [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]"); } if (PIMConfigs.Consistency_Model == Consistency.SpinLock) { //if (Config.DEBUG_MTRL) // DEBUG.WriteLine("-- Use Coherence : [" + Config.pim_config.Consistency_Model.ToString() + "]"); Coherence.spin_lock.setlock(peek.actual_addr); //when pim units start to perform, flush all relative data in the host core if (!Coherence.flush(peek.block_addr)) { Coherence.spin_lock.relese_lock(peek.actual_addr); DEBUG.WriteLine("-- Waiting Host cores flushing data : [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]"); continue; } send_queue[MemorySelector.get_id(wait_queue[i].actual_addr)].Enqueue(transfer(wait_queue[i])); wait_queue.RemoveAt(i); i--; if (Config.DEBUG_MTRL) { DEBUG.WriteLine("-- Sent ProcRequest : [" + peek.type + "] [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]"); } } } } if (Config.DEBUG_MTRL) { DEBUG.WriteLine(); } }
public void write(ref BusPacket busPacket) { //TODO: move all the error checking to BusPacket so once we have a bus packet, // we know the fields are all legal if (busPacket.column >= Config.dram_config.NUM_COLS) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("== Error - Bus Packet column " + busPacket.column + " out of bounds"); } Environment.Exit(-1); } // head of the list we need to search DataStruct rowHeadNode = rowEntries[(int)busPacket.column]; DataStruct foundNode = null; if ((foundNode = searchForRow((int)busPacket.row, rowHeadNode)) == null) { //not found DataStruct newRowNode = new DataStruct(); //insert at the head for speed //TODO: Optimize this data structure for speedier lookups? newRowNode.row = (int)busPacket.row; newRowNode.data = busPacket.data; rowEntries[(int)busPacket.column].AddFirst(newRowNode); } else { // found it, just plaster in the new data foundNode.data = busPacket.data; if (Config.dram_config.DEBUG_BANKS) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(" -- Bank " + busPacket.bank + " writing to physical address 0x" + busPacket.physicalAddress.ToString("x") + ":"); } busPacket.printData(); if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(""); } } } }
public void enqueue(BusPacket newBusPacket) { uint rank = newBusPacket.rank; uint bank = newBusPacket.bank; if (Config.dram_config.queuingStructure == QueuingStructure.PerRank) { queues[(int)rank][0].Add(newBusPacket); if (queues[(int)rank][0].Count() > Config.dram_config.CMD_QUEUE_DEPTH) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("== Error - Enqueued more than allowed in command queue"); } if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(" Need to call .hasRoomFor(int numberToEnqueue, unsigned rank, unsigned bank) first"); } Environment.Exit(1); } } else if (Config.dram_config.queuingStructure == QueuingStructure.PerRankPerBank) { queues[(int)rank][(int)bank].Add(newBusPacket); if (queues[(int)rank][(int)bank].Count() > Config.dram_config.CMD_QUEUE_DEPTH) { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("== Error - Enqueued more than allowed in command queue"); } if (Config.DEBUG_MEMORY) { DEBUG.WriteLine(" Need to call .hasRoomFor(int numberToEnqueue, unsigned rank, unsigned bank) first"); } Environment.Exit(1); } } else { if (Config.DEBUG_MEMORY) { DEBUG.WriteLine("== Error - Unknown queuing structure"); } Environment.Exit(1); } }
/// <summary> /// Memory Object get their requests here. /// </summary> /// <param name="pid">ID of memory objects.</param> /// <param name="req_">Processor Requests</param> /// <returns></returns> public static bool get_req(int pid, ref MemRequest req_) { if (send_queue[pid].Count() <= 0) { //if (Config.DEBUG_MTRL) // DEBUG.WriteLine(s + "Memory Controller -- Memory [" + pid + "] : Request No requests"); return(false); } req_ = send_queue[pid].Peek(); req_.pim = pim ? true : false; if (Config.DEBUG_MTRL) { DEBUG.WriteLine("-- PIM MTRL [" + pid + "] : Push Requests : [" + req_.memtype + "] [0x" + req_.address.ToString("X") + "]"); } send_queue[pid].Dequeue(); return(true); }