public static byte GetConditionCode(ConditionCode condition) { switch (condition) { case ConditionCode.Always: return Bits.b1110; case ConditionCode.Never: return Bits.b1111; case ConditionCode.Equal: return Bits.b0000; case ConditionCode.GreaterOrEqual: return Bits.b1010; case ConditionCode.GreaterThan: return Bits.b1100; case ConditionCode.LessOrEqual: return Bits.b1101; case ConditionCode.LessThan: return Bits.b1011; case ConditionCode.NotEqual: return Bits.b0001; case ConditionCode.UnsignedGreaterOrEqual: return Bits.b0010; case ConditionCode.UnsignedGreaterThan: return Bits.b1000; case ConditionCode.UnsignedLessOrEqual: return Bits.b1001; case ConditionCode.UnsignedLessThan: return Bits.b0011; case ConditionCode.NotSigned: return Bits.b0000; case ConditionCode.Signed: return Bits.b0000; case ConditionCode.Zero: return Bits.b0101; case ConditionCode.Overflow: return Bits.b0110; case ConditionCode.NoOverflow: return Bits.b0111; case ConditionCode.Positive: return Bits.b0101; default: throw new NotSupportedException(); } }
private void RewriteBcc(ConditionCode cc, FlagM flags) { emitter.Branch( emitter.Test(cc, orw.FlagGroup(flags)), ((M68kAddressOperand) di.op1).Address, RtlClass.ConditionalTransfer); }
public void Branch(ConditionCode condition, int immediate, bool is16Bit = false) { Emit(new BranchInstruction(is16Bit) { Condition = condition, Immediate = immediate, }); }
private void RewriteBxx(Pdp11Instruction instr, ConditionCode cc, FlagM flags) { this.rtlCluster.Class = RtlClass.Transfer; m.Branch( m.Test(cc, frame.EnsureFlagGroup(arch.GetFlagGroup((uint)flags))), ((AddressOperand)instr.op1).Address, RtlClass.ConditionalTransfer); }
public void Move(ConditionCode condition, int rd, int rn, bool is16Bit = false) { Emit(new MoveInstruction(is16Bit) { Condition = condition, SourceRegister = rn, DestinationRegister = rd, }); }
public void EmitBranch(ConditionCode conditionCode, int register) { Debug.Assert(register <= 0xF); uint value = 0; value |= (uint)(GetConditionCode(conditionCode) << 28); value |= (uint)0x12FFF10; value |= (uint)register; Write(value); }
public void EmitBranch(ConditionCode conditionCode, int offset, bool link) { Debug.Assert(offset <= 0xFFF); uint value = 0; value |= (uint)(GetConditionCode(conditionCode) << 28); value |= (uint)(Bits.b0101 << 25); value |= (uint)(link ? 1 : 0 << 24); value |= (uint)offset; Write(value); }
private void RewriteDbcc(ConditionCode cc, FlagM flags) { if (cc != ConditionCode.None) { emitter.Branch( emitter.Test(cc, orw.FlagGroup(flags)), di.Address + 4, RtlClass.ConditionalTransfer); } var src = orw.RewriteSrc(di.op1, di.Address); emitter.Assign(src, emitter.ISub(src, 1)); emitter.Branch( emitter.Ne(src, emitter.Int32(-1)), (Address) orw.RewriteSrc(di.op2, di.Address, true), RtlClass.ConditionalTransfer); }
public static ConditionCode Negate(ConditionCode cc) { switch (cc) { case ConditionCode.UGT: return ConditionCode.ULE; case ConditionCode.ULE: return ConditionCode.UGT; case ConditionCode.ULT: return ConditionCode.UGE; case ConditionCode.GT: return ConditionCode.LE; case ConditionCode.GE: return ConditionCode.LT; case ConditionCode.LT: return ConditionCode.GE; case ConditionCode.LE: return ConditionCode.GT; case ConditionCode.UGE: return ConditionCode.ULT; case ConditionCode.NE: return ConditionCode.EQ; case ConditionCode.EQ: return ConditionCode.NE; case ConditionCode.SG: return ConditionCode.GE; case ConditionCode.NS: return ConditionCode.LT; default: throw new ArgumentException(string.Format("Don't know how to negate ConditionCode.{0}.", cc), "cc"); } }
private void RewriteBranch(bool updateLinkregister, bool toLinkRegister, ConditionCode cc) { cluster.Class = RtlClass.ConditionalTransfer; var ccrOp = instr.op1 as RegisterOperand; Expression cr; if (ccrOp != null) { cr = RewriteOperand(instr.op1); } else { cr = frame.EnsureRegister(arch.CrRegisters[0]); } if (toLinkRegister) { var dst = frame.EnsureRegister(arch.lr); if (updateLinkregister) { emitter.If(emitter.Test(cc, cr), new RtlCall(dst, 0, RtlClass.ConditionalTransfer)); } else { emitter.If(emitter.Test(cc, cr), new RtlReturn(0, 0, RtlClass.Transfer)); } } else { var dst = RewriteOperand(ccrOp != null ? instr.op2 : instr.op1); if (updateLinkregister) { emitter.If(emitter.Test(cc, cr), new RtlCall(dst, 0, RtlClass.ConditionalTransfer)); } else { emitter.Branch(emitter.Test(cc, cr), (Address)dst, RtlClass.ConditionalTransfer); } } }
/// <summary> /// Appends the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> public void AppendInstruction(BaseInstruction instruction, ConditionCode condition) { AppendInstruction(); Node.SetInstruction(instruction, condition); }
/// <summary> /// Appends the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> /// <param name="block">The block.</param> public void AppendInstruction(BaseInstruction instruction, ConditionCode condition, BasicBlock block) { AppendInstruction(); Node.SetInstruction(instruction, condition, block); }
public BackwalkBranch(ConditionCode cc) : base(BackwalkOperator.branch, 0) { this.cc = cc; }
/// <summary> /// Floating point compare instruction. /// </summary> /// <param name="context">The context.</param> void IIRVisitor.FloatCompare(Context context) { Operand result = context.Result; Operand left = context.Operand1; Operand right = context.Operand2; ConditionCode condition = context.ConditionCode; // normalize condition switch (condition) { case ConditionCode.Equal: break; case ConditionCode.NotEqual: break; case ConditionCode.UnsignedGreaterOrEqual: condition = ConditionCode.GreaterOrEqual; break; case ConditionCode.UnsignedGreaterThan: condition = ConditionCode.GreaterThan; break; case ConditionCode.UnsignedLessOrEqual: condition = ConditionCode.LessOrEqual; break; case ConditionCode.UnsignedLessThan: condition = ConditionCode.LessThan; break; } // TODO - Move the following to its own pre-IR decomposition stage for this instruction // Swap, if necessary, the operands to place register operand first than memory operand // otherwise the memory operand will have to be loaded into a register if ((condition == ConditionCode.Equal || condition == ConditionCode.NotEqual) && left.IsMemoryAddress && !right.IsMemoryAddress) { // swap order of operands to move var t = left; left = right; right = t; } Context before = context.InsertBefore(); // Compare using the smallest precision if (left.IsR4 && right.IsR8) { Operand rop = AllocateVirtualRegister(TypeSystem.BuiltIn.R4); before.SetInstruction(X86.Cvtsd2ss, rop, right); right = rop; } if (left.IsR8 && right.IsR4) { Operand rop = AllocateVirtualRegister(TypeSystem.BuiltIn.R4); before.SetInstruction(X86.Cvtsd2ss, rop, left); left = rop; } X86Instruction instruction = null; InstructionSize size = InstructionSize.None; if (left.IsR4) { instruction = X86.Ucomiss; size = InstructionSize.Size32; } else { instruction = X86.Ucomisd; size = InstructionSize.Size64; } switch (condition) { case ConditionCode.Equal: { // a==b // mov eax, 1 // ucomisd xmm0, xmm1 // jp L3 // jne L3 // ret //L3: // mov eax, 0 var newBlocks = CreateNewBlockContexts(2); Context nextBlock = Split(context); context.SetInstruction(X86.Mov, result, Operand.CreateConstant(TypeSystem, 1)); context.AppendInstruction(instruction, size, null, left, right); context.AppendInstruction(X86.Branch, ConditionCode.Parity, newBlocks[1].Block); context.AppendInstruction(X86.Jmp, newBlocks[0].Block); newBlocks[0].AppendInstruction(X86.Branch, ConditionCode.NotEqual, newBlocks[1].Block); newBlocks[0].AppendInstruction(X86.Jmp, nextBlock.Block); newBlocks[1].AppendInstruction(X86.Mov, result, ConstantZero); newBlocks[1].AppendInstruction(X86.Jmp, nextBlock.Block); break; } case ConditionCode.NotEqual: { // a!=b // mov eax, 1 // ucomisd xmm0, xmm1 // jp L5 // setne al // movzx eax, al //L5: var newBlocks = CreateNewBlockContexts(1); Context nextBlock = Split(context); context.SetInstruction(X86.Mov, result, Operand.CreateConstant(TypeSystem, 1)); context.AppendInstruction(instruction, size, null, left, right); context.AppendInstruction(X86.Branch, ConditionCode.Parity, nextBlock.Block); context.AppendInstruction(X86.Jmp, newBlocks[0].Block); newBlocks[0].AppendInstruction(X86.Setcc, ConditionCode.NotEqual, result); newBlocks[0].AppendInstruction(X86.Movzx, result, result); newBlocks[0].AppendInstruction(X86.Jmp, nextBlock.Block); break; } case ConditionCode.LessThan: { // a<b // mov eax, 0 // ucomisd xmm1, xmm0 // seta al context.SetInstruction(X86.Mov, result, ConstantZero); context.AppendInstruction(instruction, size, null, right, left); context.AppendInstruction(X86.Setcc, ConditionCode.UnsignedGreaterThan, result); break; } case ConditionCode.GreaterThan: { // a>b // mov eax, 0 // ucomisd xmm0, xmm1 // seta al context.SetInstruction(X86.Mov, result, ConstantZero); context.AppendInstruction(instruction, size, null, left, right); context.AppendInstruction(X86.Setcc, ConditionCode.UnsignedGreaterThan, result); break; } case ConditionCode.LessOrEqual: { // a<=b // mov eax, 0 // ucomisd xmm1, xmm0 // setae al context.SetInstruction(X86.Mov, result, ConstantZero); context.AppendInstruction(instruction, size, null, right, left); context.AppendInstruction(X86.Setcc, ConditionCode.UnsignedGreaterOrEqual, result); break; } case ConditionCode.GreaterOrEqual: { // a>=b // mov eax, 0 // ucomisd xmm0, xmm1 // setae al context.SetInstruction(X86.Mov, result, ConstantZero); context.AppendInstruction(instruction, size, null, left, right); context.AppendInstruction(X86.Setcc, ConditionCode.UnsignedGreaterOrEqual, result); break; } } }
/// <summary> /// Sets the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> /// <param name="result">The result.</param> /// <param name="operand1">The operand1.</param> public void SetInstruction(BaseInstruction instruction, ConditionCode condition, Operand result, Operand operand1) { Node.SetInstruction(instruction, condition, result, operand1); }
/// <summary> /// Sets the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> /// <param name="updateStatus">if set to <c>true</c> [update status].</param> /// <param name="result">The result.</param> /// <param name="operand1">The operand1.</param> /// <param name="operand2">The operand2.</param> public void SetInstruction(BaseInstruction instruction, ConditionCode condition, bool updateStatus, Operand result, Operand operand1, Operand operand2) { Node.SetInstruction(instruction, condition, updateStatus, result, operand1, operand2); }
private Expression CreateTestCondition(ConditionCode cc, Opcode opcode) { var grf = orw.FlagGroup(IntelInstruction.UseCc(opcode)); var tc = new TestCondition(cc, grf); return tc; }
/// <summary> /// Sets the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> public void SetInstruction(BaseInstruction instruction, ConditionCode condition) { Node.SetInstruction(instruction, condition); }
private bool IntegerOperation(BaseInstruction instruction, ulong operand1, ulong operand2, ConditionCode conditionCode, out ulong result) { if (instruction == IRInstruction.AddSigned || instruction == IRInstruction.AddUnsigned) { result = operand1 + operand2; return(true); } else if (instruction == IRInstruction.SubSigned || instruction == IRInstruction.SubUnsigned) { result = operand1 - operand2; return(true); } else if (instruction == IRInstruction.MulUnsigned || instruction == IRInstruction.MulSigned) { result = operand1 * operand2; return(true); } else if (instruction == IRInstruction.DivUnsigned && operand2 != 0) { result = operand1 / operand2; return(true); } else if (instruction == IRInstruction.DivSigned && operand2 != 0) { result = (ulong)((long)operand1 / (long)operand2); return(true); } else if (instruction == IRInstruction.RemUnsigned && operand2 != 0) { result = operand1 % operand2; return(true); } else if (instruction == IRInstruction.RemSigned && operand2 != 0) { result = (ulong)((long)operand1 % (long)operand2); return(true); } else if (instruction == IRInstruction.ArithmeticShiftRight) { result = (ulong)(((long)operand1) >> (int)operand2); return(true); } else if (instruction == IRInstruction.ShiftRight) { result = operand1 >> (int)operand2; return(true); } else if (instruction == IRInstruction.ShiftLeft) { result = operand1 << (int)operand2; return(true); } else if (instruction == IRInstruction.IntegerCompare) { bool?compare = Compare(operand1, operand2, conditionCode); if (compare.HasValue) { result = compare.Value ? 1u : 0u; return(true); } } result = 0; return(false); }
private void RewriteConditionalGoto(ConditionCode cc, MachineOperand op1) { emitter.Branch(CreateTestCondition(cc, instrCur.code), OperandAsCodeAddress(op1), RtlClass.ConditionalTransfer); }
private void Branch(ConditionCode code, MachineOperand op) { this.iclass = InstrClass.ConditionalTransfer; m.Branch(m.Test(code, orw.AluRegister(Registers.FPUF)), OperandAsCodeAddress(op)!, InstrClass.ConditionalTransfer); }
private void RewriteConditionalGoto(ConditionCode cc, MachineOperand op1) { iclass = InstrClass.ConditionalTransfer; m.Branch(CreateTestCondition(cc, instrCur.Mnemonic), OperandAsCodeAddress(op1) !, InstrClass.ConditionalTransfer); }
private void RewriteBranch(ConditionCode cc, Identifier grf) { var target = (Address)RewriteSrc(instr.Operands[0]); m.Branch(m.Test(cc, grf), target, InstrClass.ConditionalTransfer); }
/// <summary> /// Appends the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> /// <param name="updateStatus">if set to <c>true</c> [update status].</param> /// <param name="result">The result.</param> /// <param name="operand1">The operand1.</param> public void AppendInstruction(BaseInstruction instruction, ConditionCode condition, bool updateStatus, Operand result, Operand operand1) { AppendInstruction(); Node.SetInstruction(instruction, condition, updateStatus, result, operand1); }
public void BranchCc(ConditionCode cc, string label) { Identifier f; switch (cc) { case ConditionCode.EQ: case ConditionCode.NE: f = Flags("Z"); break; default: throw new ArgumentOutOfRangeException("Condition code: " + cc); } branchBlock = BlockOf(label); Emit(new Branch(new TestCondition(cc, f), branchBlock)); TerminateBlock(); }
/// <summary> /// Appends the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="result">The result.</param> /// <param name="operand1">The operand1.</param> /// <param name="operand2">The operand2.</param> public void AppendInstruction(BaseInstruction instruction, ConditionCode condition, Operand result, Operand operand1, Operand operand2) { AppendInstruction(); Node.SetInstruction(instruction, condition, result, operand1, operand2); }
public TwainException(string message, TwainResult returnCode, ConditionCode conditionCode) : this(message, null) { ReturnCode = returnCode; ConditionCode = conditionCode; }
/// <summary> /// Sets the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> /// <param name="block">The block.</param> public void SetInstruction(BaseInstruction instruction, ConditionCode condition, BasicBlock block) { Node.SetInstruction(instruction, condition, block); }
public void EmitMultiplyWithAccumulate(ConditionCode conditionCode, bool setCondition, int firstRegister, int destinationRegister, int secondRegister, int accumulateRegister) { Debug.Assert(destinationRegister <= 0xF); Debug.Assert(secondRegister <= 0xF); Debug.Assert(firstRegister <= 0xF); uint value = 0; value |= (uint)(GetConditionCode(conditionCode) << 28); value |= (uint)(1 << 21); value |= (uint)(setCondition ? 1 : 0 << 20); value |= (uint)(destinationRegister << 16); value |= (uint)(firstRegister << 12); value |= (uint)(secondRegister << 8); value |= (uint)(Bits.b1001 << 4); value |= (uint)accumulateRegister; Write(value); }
/// <summary> /// Sets the instruction. /// </summary> /// <param name="instruction">The instruction.</param> /// <param name="condition">The condition.</param> /// <param name="result">The result.</param> /// <param name="operand1">The operand1.</param> /// <param name="operand2">The operand2.</param> /// <param name="block">The block.</param> public void SetInstruction(BaseInstruction instruction, ConditionCode condition, Operand result, Operand operand1, Operand operand2, BasicBlock block) { Node.SetInstruction(instruction, condition, result, operand1, operand2, block); }
public void EmitSingleDataTransfer(ConditionCode conditionCode, Indexing indexing, OffsetDirection offsetDirection, TransferSize transferSize, WriteBack writeBack, TransferType transferType, int firstRegister, int destinationRegister, ShiftType secondShiftType, int secondRegister) { Debug.Assert(destinationRegister <= 0xF); Debug.Assert(firstRegister <= 0xF); Debug.Assert(secondRegister <= 0xF); uint value = 0; value |= (uint)(GetConditionCode(conditionCode) << 28); value |= (uint)(1 << 26); value |= (uint)(1 << 25); value |= (uint)((indexing == Indexing.Post ? 0 : 1) << 24); value |= (uint)((transferSize == TransferSize.Word ? 0 : 1) << 23); value |= (uint)((offsetDirection == OffsetDirection.Down ? 0 : 1) << 22); value |= (uint)((writeBack == WriteBack.NoWriteBack ? 0 : 1) << 21); value |= (uint)((transferType == TransferType.Store ? 0 : 1) << 20); value |= (uint)(destinationRegister << 12); value |= (uint)(firstRegister << 16); value |= (uint)(GetShiftTypeCode(secondShiftType) << 4); value |= (uint)secondRegister; Write(value); }
private static bool? Compare(VariableState operand1, VariableState operand2, ConditionCode conditionCode) { switch (conditionCode) { case ConditionCode.Equal: return operand1.ConstantUnsignedLongInteger == operand2.ConstantUnsignedLongInteger; case ConditionCode.NotEqual: return operand1.ConstantUnsignedLongInteger != operand2.ConstantUnsignedLongInteger; case ConditionCode.GreaterOrEqual: return operand1.ConstantUnsignedLongInteger >= operand2.ConstantUnsignedLongInteger; case ConditionCode.GreaterThan: return operand1.ConstantUnsignedLongInteger > operand2.ConstantUnsignedLongInteger; case ConditionCode.LessOrEqual: return operand1.ConstantUnsignedLongInteger <= operand2.ConstantUnsignedLongInteger; case ConditionCode.LessThan: return operand1.ConstantUnsignedLongInteger < operand2.ConstantUnsignedLongInteger; case ConditionCode.Always: return true; case ConditionCode.Never: return false; // unknown integer comparison default: return null; } }
public ConditionalJumpInstruction(ConditionCode condition, Word wordDisplacement) { Condition = condition; }
private void RewriteLoop(FlagM useFlags, ConditionCode cc) { Identifier cx = orw.AluRegister(Registers.ecx, instrCur.dataWidth); emitter.Assign(cx, emitter.ISub(cx, 1)); if (useFlags != 0) { emitter.Branch( new BinaryExpression(Operator.Cand, PrimitiveType.Bool, new TestCondition(cc, orw.FlagGroup(useFlags)), emitter.Ne0(cx)), OperandAsCodeAddress(instrCur.op1), RtlClass.ConditionalTransfer); } else { emitter.Branch(emitter.Ne0(cx), OperandAsCodeAddress(instrCur.op1), RtlClass.ConditionalTransfer); } }
public void EmitInstructionWithImmediate(ConditionCode conditionCode, byte opcode, bool setCondition, int firstRegister, int destinationRegister, int rotate, int immediate) { Debug.Assert(opcode <= 0xF); Debug.Assert(destinationRegister <= 0xF); Debug.Assert(firstRegister <= 0xF); Debug.Assert(rotate <= 0xF); Debug.Assert(immediate <= 0xFF); uint value = 0; value |= (uint)(GetConditionCode(conditionCode) << 28); value |= (uint)(0x1 << 25); value |= (uint)(opcode << 21); value |= (uint)(setCondition ? 1 : 0 << 20); value |= (uint)(firstRegister << 16); value |= (uint)(destinationRegister << 12); value |= (uint)(rotate << 8); value |= (uint)immediate; Write(value); }
/// <summary> /// Clears this instance. /// </summary> public void Clear() { this.Label = -1; this.Instruction = null; this.Operand1 = null; this.Operand2 = null; this.Operand3 = null; this.Result = null; this.Result2 = null; this.packed = 0; this.additionalOperands = null; this.BranchTargets = null; this.Other = null; this.BranchHint = false; this.ConditionCode = ConditionCode.Undefined; }
public void EmitInstructionWithRegister(ConditionCode conditionCode, byte opcode, bool setCondition, int firstRegister, int destinationRegister, ShiftType secondShiftType, int secondRegister) { Debug.Assert(opcode <= 0xF); Debug.Assert(destinationRegister <= 0xF); Debug.Assert(firstRegister <= 0xF); Debug.Assert(secondRegister <= 0xF); uint value = 0; value |= (uint)(GetConditionCode(conditionCode) << 28); value |= (uint)(0x0 << 25); value |= (uint)(opcode << 21); value |= (uint)(setCondition ? 1 : 0 << 20); value |= (uint)(firstRegister << 16); value |= (uint)(destinationRegister << 12); value |= (uint)(GetShiftTypeCode(secondShiftType) << 4); value |= (uint)secondRegister; Write(value); }
/// <summary> /// Gets the condition string. /// </summary> /// <param name="conditioncode">The conditioncode.</param> /// <returns></returns> protected string GetConditionString(ConditionCode conditioncode) { switch (conditioncode) { case ConditionCode.Equal: return @"equal"; case ConditionCode.GreaterOrEqual: return @"greater or equal"; case ConditionCode.GreaterThan: return @"greater"; case ConditionCode.LessOrEqual: return @"less or equal"; case ConditionCode.LessThan: return @"less"; case ConditionCode.NotEqual: return @"not equal"; case ConditionCode.UnsignedGreaterOrEqual: return @"greater or equal (U)"; case ConditionCode.UnsignedGreaterThan: return @"greater (U)"; case ConditionCode.UnsignedLessOrEqual: return @"less or equal (U)"; case ConditionCode.UnsignedLessThan: return @"less (U)"; case ConditionCode.NotSigned: return @"not signed"; case ConditionCode.Signed: return @"signed"; case ConditionCode.Zero: return @"zero"; case ConditionCode.NotZero: return @"not zero"; case ConditionCode.Parity: return @"parity"; case ConditionCode.NoParity: return @"no parity"; case ConditionCode.Carry: return @"carry"; case ConditionCode.NoCarry: return @"no carry"; case ConditionCode.Always: return @"always"; default: throw new NotSupportedException(); } }
private static BaseOpcode ConvertToOpcode(X86Instruction instruction, ConditionCode conditionCode) { if (instruction == X86.Adc) { return(Opcode.Adc); } if (instruction == X86.Add) { return(Opcode.Add); } if (instruction == X86.Addsd) { return(Opcode.Addsd); } if (instruction == X86.Addss) { return(Opcode.Addss); } if (instruction == X86.And) { return(Opcode.And); } //if (instruction == X86.Break) return Opcode.Break; if (instruction == X86.Call) { return(Opcode.Call); } if (instruction == X86.Cdq) { return(Opcode.Cdq); } //if (instruction == X86.Cld) return Opcode.Cld; if (instruction == X86.Cli) { return(Opcode.Cli); } if (instruction == X86.Cmp) { return(Opcode.Cmp); } if (instruction == X86.CmpXchg) { return(Opcode.CmpXchg); } if (instruction == X86.Comisd) { return(Opcode.Comisd); } if (instruction == X86.Comiss) { return(Opcode.Comiss); } if (instruction == X86.CpuId) { return(Opcode.Cpuid); } if (instruction == X86.Cvtsd2ss) { return(Opcode.Cvtsd2ss); } if (instruction == X86.Cvtsi2sd) { return(Opcode.Cvtsi2sd); } if (instruction == X86.Cvtsi2ss) { return(Opcode.Cvtsi2ss); } if (instruction == X86.Cvtss2sd) { return(Opcode.Cvtss2sd); } if (instruction == X86.Cvttsd2si) { return(Opcode.Cvttsd2si); } if (instruction == X86.Cvttss2si) { return(Opcode.Cvttss2si); } if (instruction == X86.Dec) { return(Opcode.Dec); } if (instruction == X86.Div) { return(Opcode.Div); } if (instruction == X86.Divsd) { return(Opcode.Divsd); } if (instruction == X86.Divss) { return(Opcode.Divss); } if (instruction == X86.FarJmp) { return(Opcode.FarJmp); } if (instruction == X86.Fld) { return(Opcode.Fld); } if (instruction == X86.Hlt) { return(Opcode.Hlt); } if (instruction == X86.IDiv) { return(Opcode.Idiv); } if (instruction == X86.IMul) { return(Opcode.Imul); } if (instruction == X86.In) { return(Opcode.In); } if (instruction == X86.Inc) { return(Opcode.Inc); } //if (instruction == X86.Int) return Opcode.Int; //if (instruction == X86.Invlpg) return Opcode.Invlpg; if (instruction == X86.IRetd) { return(Opcode.Iretd); } if (instruction == X86.Jmp) { return(Opcode.Jmp); } if (instruction == X86.Lea) { return(Opcode.Lea); } //if (instruction == X86.Leave) return Opcode.Leave; if (instruction == X86.Lgdt) { return(Opcode.Lgdt); } if (instruction == X86.Lidt) { return(Opcode.Lidt); } //if (instruction == X86.Lock) return Opcode.Lock; if (instruction == X86.Mov) { return(Opcode.Mov); } if (instruction == X86.Movsd) { return(Opcode.Movsd); } if (instruction == X86.Movss) { return(Opcode.Movss); } if (instruction == X86.Movsx) { return(Opcode.Movsx); } if (instruction == X86.Movzx) { return(Opcode.Movzx); } if (instruction == X86.Mul) { return(Opcode.Mul); } if (instruction == X86.Mulsd) { return(Opcode.Mulsd); } if (instruction == X86.Mulss) { return(Opcode.Mulss); } if (instruction == X86.Neg) { return(Opcode.Neg); } if (instruction == X86.Nop) { return(Opcode.Nop); } if (instruction == X86.Not) { return(Opcode.Not); } if (instruction == X86.Or) { return(Opcode.Or); } if (instruction == X86.Out) { return(Opcode.Out); } //if (instruction == X86.Pause) return Opcode.Pause; if (instruction == X86.Pop) { return(Opcode.Pop); } if (instruction == X86.Popad) { return(Opcode.Popad); } if (instruction == X86.Popfd) { return(Opcode.Popfd); } if (instruction == X86.Push) { return(Opcode.Push); } if (instruction == X86.Pushad) { return(Opcode.Pushad); } if (instruction == X86.Pushfd) { return(Opcode.Pushfd); } if (instruction == X86.Rcr) { return(Opcode.Rcr); } //if (instruction == X86.Rdmsr) return Opcode.Rdmsr; //if (instruction == X86.Rdpmc) return Opcode.Rdpmc; //if (instruction == X86.Rdtsc) return Opcode.Rdtsc; //if (instruction == X86.Rep) return Opcode.Rep; if (instruction == X86.Ret) { return(Opcode.Ret); } if (instruction == X86.Roundsd) { return(Opcode.Roundsd); } if (instruction == X86.Roundss) { return(Opcode.Roundss); } if (instruction == X86.Sar) { return(Opcode.Sar); } if (instruction == X86.Sbb) { return(Opcode.Sbb); } if (instruction == X86.Shl) { return(Opcode.Shl); } if (instruction == X86.Shld) { return(Opcode.Shld); } if (instruction == X86.Shr) { return(Opcode.Shr); } if (instruction == X86.Shrd) { return(Opcode.Shrd); } if (instruction == X86.Sti) { return(Opcode.Sti); } if (instruction == X86.Pause) { return(Opcode.Pause); } //if (instruction == X86.Stos) return Opcode.Stos; if (instruction == X86.Sub) { return(Opcode.Sub); } if (instruction == X86.Subsd) { return(Opcode.Subsd); } if (instruction == X86.Subss) { return(Opcode.Subss); } if (instruction == X86.Xchg) { return(Opcode.Xchg); } if (instruction == X86.Xor) { return(Opcode.Xor); } if (instruction == X86.PXor) { return(Opcode.Pxor); } if (instruction == X86.MovCR) { return(Opcode.Mov); } if (instruction == X86.MovUPS) { return(Opcode.Movups); } if (instruction == X86.MovAPS) { return(Opcode.Movaps); } if (instruction == X86.Ucomisd) { return(Opcode.Ucomisd); } if (instruction == X86.Ucomiss) { return(Opcode.Ucomiss); } if (instruction == X86.Test) { return(Opcode.Test); } if (instruction == X86.Setcc) { return(ConvertSetInstruction(conditionCode)); } if (instruction == X86.Branch) { return(ConvertBranchInstruction(conditionCode)); } if (instruction == X86.Cmovcc) { return(ConvertConditionalMoveInstruction(conditionCode)); } if (instruction == X86.Bts) { return(Opcode.Bts); } if (instruction == X86.Btr) { return(Opcode.Btr); } if (instruction == X86.Lock) { return(Opcode.Lock); } if (instruction == X86.Break) { return(Opcode.InternalBreak); } return(null); }